Processor Users Manual

MOTOROLA Illustrations xxxv
ILLUSTRATIONS
Figure
Number
Title
Page
Number
9-3 System Clock Control Register (SCCR).................................................................... 9-8
9-4 System Clock Mode Register (SCMR)...................................................................... 9-9
9-5 Relationships of SCMR Parameters ........................................................................ 9-10
10-1 Dual-Bus Architecture ............................................................................................. 10-3
10-2 Memory Controller Machine Selection ................................................................... 10-6
10-3 Simple System Configuration.................................................................................. 10-7
10-4 Basic Memory Controller Operation ....................................................................... 10-8
10-5 Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer ............ 10-13
10-6 Base Registers (BRx) ............................................................................................ 10-14
10-7 Option Registers (ORx)ÑSDRAM Mode ............................................................ 10-16
10-8 ORx ÑGPCM Mode............................................................................................. 10-18
10-9 ORxÑUPM Mode................................................................................................. 10-20
10-10 60x/Local SDRAM Mode Register (PSDMR/LSDMR) ....................................... 10-21
10-11 Machine x Mode Registers (MxMR)..................................................................... 10-26
10-12 Memory Data Register (MDR).............................................................................. 10-29
10-13 Memory Address Register (MAR) ........................................................................ 10-29
10-14 60x Bus-Assigned UPM Refresh Timer (PURT) .................................................. 10-30
10-15 Local Bus-Assigned UPM Refresh Timer (LURT)............................................... 10-30
10-16 60x Bus-Assigned SDRAM Refresh Timer (PSRT) ............................................. 10-31
10-17 Local Bus-Assigned SDRAM Refresh Timer (LSRT).......................................... 10-32
10-18 Memory Refresh Timer Prescaler Register (MPTPR)........................................... 10-32
10-19 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)............ 10-34
10-20 PRETOACT = 2 (2 Clock Cycles) ........................................................................ 10-39
10-21 ACTTORW = 2 (2 Clock Cycles) ......................................................................... 10-39
10-22 CL = 2 (2 Clock Cycles)........................................................................................ 10-40
10-23 LDOTOPRE = 2 (-2 Clock Cycles)....................................................................... 10-40
10-24 WRC = 2 (2 Clock Cycles).................................................................................... 10-41
10-25 RFRC = 4 (6 Clock Cycles)................................................................................... 10-41
10-26 EAMUX = 1 .......................................................................................................... 10-42
10-27 BUFCMD = 1 ........................................................................................................ 10-42
10-28 SDRAM Single-Beat Read, Page Closed, CL = 3................................................. 10-43
10-29 SDRAM Single-Beat Read, Page Hit, CL = 3....................................................... 10-43
10-30 SDRAM Two-Beat Burst Read, Page Closed, CL = 3 .......................................... 10-43
10-31 SDRAM Four-Beat Burst Read, Page Miss, CL = 3 ............................................. 10-44
10-32 SDRAM Single-Beat Write, Page Hit ................................................................... 10-44
10-33 SDRAM Three-Beat Burst Write, Page Closed .................................................... 10-44
10-34 SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 .......................................... 10-45
10-35 SDRAM Write-after-Write Pipelined, Page Hit.................................................... 10-45
10-36 SDRAM Read-after-Write Pipelined, Page Hit..................................................... 10-45
10-37 SDRAM Mode-Set Command Timing.................................................................. 10-46
10-38 Mode Data Bit Settings.......................................................................................... 10-47
10-39 SDRAM Bank-Staggered CBR Refresh Timing ................................................... 10-48
10-40 GPCM-to-SRAM ConÞguration............................................................................ 10-52