Processor Users Manual

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-15
Part III. The Hardware Interface
347 IO.ctl g89.ctl Ñ Ñ
348 i.obs psdval_b io Ñ
349 o.pin psdval_b io g130.ctl
350 IO.ctl g130.ctl Ñ Ñ
351 i.obs dbb_b_irq3_b io Ñ
352 o.pin dbb_b_irq3_b io g129.ctl
353 IO.ctl g129.ctl Ñ Ñ
354 i.obs dbg_b io Ñ
355 o.pin dbg_b io g128.ctl
356 IO.ctl g128.ctl Ñ Ñ
357 i.obs spare4 io Ñ
358 o.pin spare4 io g127.ctl
359 IO.ctl g127.ctl Ñ Ñ
360 i.obs cpu_bg_b_baddr31_irq5_b io Ñ
361 o.pin cpu_bg_b_baddr31_irq5_b io g126.ctl
362 IO.ctl g126.ctl Ñ Ñ
363 i.obs wt_b_baddr30_irq3_b io Ñ
364 o.pin wt_b_baddr30_irq3_b io g125.ctl
365 IO.ctl g125.ctl Ñ Ñ
366 i.obs ci_b_baddr29_irq2_b io Ñ
367 o.pin ci_b_baddr29_irq2_b io g124.ctl
368 IO.ctl g124.ctl Ñ Ñ
369 o.pin baddr[28] o Ñ
370 o.pin baddr[27] o Ñ
371 o.pin ale o Ñ
372 i.obs irq0_b_nmi_out_b io Ñ
373 o.pin irq0_b_nmi_out_b io g120.ctl
374 IO.ctl g120.ctl Ñ Ñ
375 o.pin cpu_dbg_b o Ñ
376 i.obs a[31] io Ñ
377 o.pin a[31] io g111.ctl
378 i.obs a[30] io Ñ
379 o.pin a[30] io g111.ctl
380 i.obs a[29] io Ñ
381 o.pin a[29] io g111.ctl
382 i.obs a[28] io Ñ
383 o.pin a[28] io g111.ctl
384 i.obs a[27] io Ñ
385 o.pin a[27] io g111.ctl
Table 12-2. Boundary Scan Bit Definition (Continued)
Bit Cell Type Pin/Cell Name Pin Type Output Control Cell