Processor Users Manual

MOTOROLA Illustrations xli
ILLUSTRATIONS
Figure
Number
Title
Page
Number
26-19 SMC GCI Event Register (SMCE)/Mask Register (SMCM)................................ 26-34
27-1 BD Structure for One MCC..................................................................................... 27-3
27-2 Super Channel Table Entry...................................................................................... 27-5
27-3 Transmitter Super Channel Example....................................................................... 27-6
27-4 Receiver Super Channel with Slot Synchronization Example ................................ 27-7
27-5 Receiver Super Channel without Slot Synchronization Example ........................... 27-7
27-6 TSTATE High Byte................................................................................................. 27-9
27-7 INTMSK Mask Bits............................................................................................... 27-10
27-8 Channel Mode Register (CHAMR) ....................................................................... 27-10
27-9 Rx Internal State (RSTATE) High Byte................................................................ 27-12
27-10 Channel Mode Register (CHAMR)ÑTransparent Mode...................................... 27-14
27-11 SI MCC Configuration Register (MCCF) ............................................................. 27-15
27-12 Interrupt Circular Table ......................................................................................... 27-17
27-13 MCC Event Register (MCCE)/Mask Register (MCCM) ...................................... 27-18
27-14 Interrupt Circular Table Entry ............................................................................... 27-20
27-15 MCC Receive Buffer Descriptor (RxBD) ............................................................. 27-21
27-16 MCC Transmit Buffer Descriptor (TxBD) ............................................................ 27-23
28-1 FCC Block Diagram ................................................................................................ 28-3
28-2 General FCC Mode Register (GFMR) .................................................................... 28-3
28-3 FCC Memory Structure ........................................................................................... 28-9
28-4 Buffer Descriptor Format ........................................................................................ 28-9
28-5 Function Code Register (FCRx) ............................................................................ 28-13
28-6 Output Delay from RTS Asserted.......................................................................... 28-16
28-7 Output Delay from CTS Asserted.......................................................................... 28-17
28-8 CTS Lost................................................................................................................ 28-18
28-9 Using CD to Control Reception............................................................................. 28-19
29-1 APC Scheduling Table Mechanism....................................................................... 29-10
29-2 VBR Pacing Using the GCRA (Leaky Bucket Algorithm) ................................... 29-12
29-3 External CAM Data Input Fields........................................................................... 29-14
29-4 External CAM Output Fields................................................................................. 29-14
29-5 Address Compression Mechanism ........................................................................ 29-16
29-6 General VCOFFSET Formula for Contiguous VCLTs ......................................... 29-17
29-7 VP Pointer Address Compression ......................................................................... 29-18
29-8 VC Pointer Address Compression ......................................................................... 29-18
29-9 ATM Address Recognition Flowchart................................................................... 29-19
29-10 MPC8260Õs ABR Basic Model ............................................................................. 29-20
29-11 ABR Transmit Flow .............................................................................................. 29-22
29-12 ABR Transmit Flow (Continued) .......................................................................... 29-23
29-13 ABR Transmit Flow (Continued) .......................................................................... 29-24
29-14 ABR Receive Flow ................................................................................................ 29-25
29-15 Rate Format for RM Cells ..................................................................................... 29-26
29-16 Rate Formula for RM Cells ................................................................................... 29-26
29-17 Performance Monitoring Cell Structure (FMCs and BRCs) ................................. 29-29