Processor Users Manual

12-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
620 i.obs dp7_cse1_irq7_b io Ñ
621 o.pin dp7_cse1_irq7_b io g99.ctl
622 IO.ctl g99.ctl Ñ Ñ
623 i.obs dp6_cse0_irq6_b io Ñ
624 o.pin dp6_cse0_irq6_b io g98.ctl
625 IO.ctl g98.ctl Ñ Ñ
626 i.obs dp5_tben_irq5_b io Ñ
627 o.pin dp5_tben_irq5_b io g97.ctl
628 IO.ctl g97.ctl Ñ Ñ
629 i.obs dp4_irq4_b io Ñ
630 o.pin dp4_irq4_b io g96.ctl
631 IO.ctl g96.ctl Ñ Ñ
632 i.obs dp3_irq3_b io Ñ
633 o.pin dp3_irq3_b io g95.ctl
634 IO.ctl g95.ctl Ñ Ñ
635 i.obs dp2_tlbisync_b_irq2_b io Ñ
636 o.pin dp2_tlbisync_b_irq2_b io g94.ctl
637 IO.ctl g94.ctl Ñ Ñ
638 i.obs dp1_irq1_b io Ñ
639 o.pin dp1_irq1_b io g93.ctl
640 IO.ctl g93.ctl Ñ Ñ
641 i.obs dp0_rsrv_b io Ñ
642 o.pin dp0_rsrv_b io g92.ctl
643 IO.ctl g92.ctl Ñ Ñ
644 i.obs ta_b io Ñ
645 o.pin ta_b io g131.ctl
646 IO.ctl g131.ctl Ñ Ñ
647 o.pin sdamux_gpl5 o Ñ
648 i.obs gta_b_upwait_gpl4_pbs io Ñ
649 o.pin gta_b_upwait_gpl4_pbs io g87.ctl
650 IO.ctl g87.ctl Ñ Ñ
651 o.pin sdcas_b_gpl3 o Ñ
652 o.pin oe_b_sdras_b_gpl2 o Ñ
653 o.pin sdwe_b_gpl1 o Ñ
654 o.pin sda10_gpl0 o Ñ
655 o.pin we_dqm_bs_b[7] o Ñ
656 o.pin we_dqm_bs_b[6] o Ñ
657 o.pin we_dqm_bs_b[5] o Ñ
658 o.pin we_dqm_bs_b[4] o Ñ
Table 12-2. Boundary Scan Bit Definition (Continued)
Bit Cell Type Pin/Cell Name Pin Type Output Control Cell