Processor Users Manual

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-23
Part III. The Hardware Interface
659 o.pin we_dqm_bs_b[3] o Ñ
660 o.pin we_dqm_bs_b[2] o Ñ
661 o.pin we_dqm_bs_b[1] o Ñ
662 o.pin bctl0_b o Ñ
663 o.pin we_dqm_bs_b[0] o Ñ
664 o.pin lsdamux_gpl5 o Ñ
665 i.obs lgta_b_upwait_gpl4_pbs io Ñ
666 o.pin lgta_b_upwait_gpl4_pbs io g66.ctl
667 IO.ctl g66.ctl Ñ Ñ
668 o.pin lsdcas_b_gpl3 o Ñ
669 o.pin loe_b_sdras_b_gpl2 o Ñ
670 o.pin lsdwe_b_gpl1 o Ñ
671 o.pin lsda10_gpl0 o Ñ
672 o.pin lwr_b o Ñ
673 o.pin cs_b[0] o Ñ
674 o.pin cs_b[1] o Ñ
675 o.pin cs_b[2] o Ñ
676 o.pin cs_b[3] o Ñ
677 o.pin cs_b[4] o Ñ
678 o.pin cs_b[5] o Ñ
679 o.pin cs_b[6] o Ñ
680 o.pin cs_b[7] o Ñ
681 o.pin cs_b[8] o Ñ
682 o.pin cs_b[9] o Ñ
683 i.obs cs10_b_bctl1_b_dbg_dis io Ñ
684 o.pin cs10_b_bctl1_b_dbg_dis io g59.ctl
685 IO.ctl g59.ctl Ñ Ñ
686 i.obs cs11_b_ap0 io Ñ
687 o.pin cs11_b_ap0 io g60.ctl
688 IO.ctl g60.ctl Ñ Ñ
689 o.pin lwe_dqm_bs_b[3] o Ñ
690 o.pin lwe_dqm_bs_b[2] o Ñ
691 o.pin lwe_dqm_bs_b[1] o Ñ
692 o.pin lwe_dqm_bs_b[0] o Ñ
693 i.obs lcl_d_ad[0] io Ñ
694 o.pin lcl_d_ad[0] io g40.ctl
695 i.obs lcl_d_ad[5] io Ñ
696 o.pin lcl_d_ad[5] io g48.ctl
697 IO.ctl g48.ctl Ñ Ñ
Table 12-2. Boundary Scan Bit Definition (Continued)
Bit Cell Type Pin/Cell Name Pin Type Output Control Cell