Processor Users Manual

13-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part IV. Communications Processor Module

6Ð10 SBC Sub-block code. Set by the core to specify the sub-block on which the command is to operate.

Sub-block Code Page Sub-block Code Page

FCC1 10000

(for ATM: 01110)

00100 SPI 01010 01001

FCC2 10001

(for ATM: 01110)

00101 I

C 01011 01010

FCC3 10010 00110 Timer 01111 01010

SCC1 00100 00000 MCC1 11100 00111

SCC2 00101 00001 MCC2 11101 01000

SCC3 00110 00010 IDMA1 10100 00111

SCC4 00111 00011 IDMA2 10101 01000

SMC1 01000 00111 IDMA3 10110 01001

SMC2 01001 01000 IDMA4 10111 01010

RAND 01110 01010

11Ð14 Ñ Reserved

15 FLG Command semaphore ßag. Set by the core and cleared by the CP.

0 The CP is ready to receive a new command.

1 The CPCR contains a command that the CP is currently processing. The CP clears this bit at

the end of command execution or after reset.

16Ð17 Ñ Reserved

18Ð25 MCN MCC channel number. SpeciÞes the channel number in the case of an MCC command.

In FCC protocols, this Þeld contains the protocol code as follows:

0x00 HDLC

0x0A ATM

0x0C Ethernet

0x0F Transparent

26-27 Ñ Reserved

28Ð31 OPCODE Operation code. Settings are listed in Table 13-7 below.

Table 13-6. CP Command Register Field Descriptions (Continued)

Bit Name Description