Processor Users Manual

xlvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
TABLES
Table
Number
Title
Page
Number
4-21 PISCR Field Descriptions........................................................................................ 4-43
4-22 PITC Field Descriptions .......................................................................................... 4-44
4-23 PITR Field Descriptions .......................................................................................... 4-44
4-24 SIU Pins Multiplexing Control................................................................................ 4-45
5-1 Reset Causes .............................................................................................................. 5-1
5-2 Reset Actions for Each Reset Source ........................................................................ 5-2
5-3 RSR Field Descriptions ............................................................................................. 5-4
5-4 RMR Field Descriptions ............................................................................................ 5-5
5-5 RSTCONF Connections in Multiple-MPC8260 Systems ......................................... 5-6
5-6 Configuration EPROM Addresses............................................................................. 5-7
5-7 Hard Reset Configuration Word Field Descriptions ................................................. 5-8
vi Acronyms and Abbreviated Terms.........................................................................III-iii
6-1 External Signals ......................................................................................................... 6-3
7-1 DP[0Ð7] Signal Assignments................................................................................... 7-15
8-1 Terminology .............................................................................................................. 8-1
8-2 Transfer Type Encoding .......................................................................................... 8-10
8-3 Transfer Code Encoding .......................................................................................... 8-13
8-4 Transfer Size Signal Encoding ................................................................................ 8-13
8-5 Burst Ordering ......................................................................................................... 8-14
8-6 Aligned Data Transfers............................................................................................ 8-15
8-7 Unaligned Data Transfer Example (4-Byte Example)............................................. 8-16
8-8 Data Bus Requirements For Read Cycle ................................................................. 8-18
8-9 Data Bus Contents for Write Cycles........................................................................ 8-19
8-10 Address and Size State Calculations........................................................................ 8-20
8-11 Data Bus Contents for Extended Write Cycles........................................................ 8-21
8-12 Data Bus Requirements for Extended Read Cycles ................................................ 8-21
8-13 Address and Size State for Extended Transfers....................................................... 8-22
9-1 Clock Default Modes................................................................................................. 9-2
9-2 Clock Configuration Modes ...................................................................................... 9-2
9-3 Dedicated PLL Pins ................................................................................................... 9-7
9-4 SCCR Field Descriptions........................................................................................... 9-8
9-5 SCMR Field Descriptions.......................................................................................... 9-9
10-1 Number of PSDVAL Assertions Needed for TA Assertion.................................. 10-12
10-2 60x Bus Memory Controller Registers .................................................................. 10-13
10-3 BRx Field Descriptions.......................................................................................... 10-14
10-4 ORx Field Descriptions (SDRAM Mode) ............................................................. 10-16
10-5 ORxÑGPCM Mode Field Descriptions................................................................ 10-18
10-6 Option Register (ORx)ÑUPM Mode.................................................................... 10-20
10-7 PSDMR Field Descriptions ................................................................................... 10-21
10-8 LSDMR Field Descriptions ................................................................................... 10-24
10-9 Machine x Mode Registers (MxMR)..................................................................... 10-27
10-10 MDR Field Descriptions........................................................................................ 10-29
10-11 MAR Field Description ......................................................................................... 10-30