Processor Users Manual

MOTOROLA Chapter 15. CPM Multiplexing 15-13
Part IV. Communications Processor Module
Table 15-5 describes CMXFCR Þelds.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ FC1 RF1CS TF1CS Ñ FC2 RF2CS TF2CS
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11B04
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ FC3 RF3CS TF3CS Ñ
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11B06
Figure 15-10. CMX FCC Clock Route Register (CMXFCR)
Table 15-5. CMXFCR Field Descriptions
Bits Name Description
0 Ñ Reserved, should be cleared
1 FC1 DeÞnes the FCC1 connection
0 FCC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O
control register.
1 FCC1 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.
2Ð4 RF1CS Receive FCC1 clock source (NMSI mode). Ignored if FCC1 is connected to the TSA (FC1 = 1).
000 FCC1 receive clock is BRG5.
001 FCC1 receive clock is BRG6.
010 FCC1 receive clock is BRG7.
011 FCC1 receive clock is BRG8.
100 FCC1 receive clock is CLK9.
101 FCC1 receive clock is CLK10.
110 FCC1 receive clock is CLK11.
111 FCC1 receive clock is CLK12.
5Ð7 TF1CS Transmit FCC1 clock source (NMSI mode). Ignored if FCC1 is connected to the TSA (FC1 = 1).
000 FCC1 transmit clock is BRG5.
001 FCC1 transmit clock is BRG6.
010 FCC1 transmit clock is BRG7.
011 FCC1 transmit clock is BRG8.
100 FCC1 transmit clock is CLK9.
101 FCC1 transmit clock is CLK10.
110 FCC1 transmit clock is CLK11.
111 FCC1 transmit clock is CLK12.
8 Ñ Reserved, should be cleared
9 FC2 DeÞnes the FCC2 connection
0 FCC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O
control register.
1 FCC2 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.