Processor Users Manual

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-3
Part IV. Communications Processor Module
Figure 18-2. SDMA Bus Arbitration (Transaction Steal)
18.2 SDMA Registers
The only user-accessible registers associated with the SDMA are the SDMA address
registers, read-only register used for diagnostics in case of an SDMA bus error, the SDMA
status register and the SDMA mask register.
18.2.1 SDMA Status Register (SDSR)
The SDMA status register (SDSR) reports bus error events recognized by the SDMA
controller for all 26 SDMA channels and 4 IDMA channels. On recognition of a bus error
on the local or 60x buses, the SDMA sets its corresponding SDSR bit. The SDSR is a
memory-mapped register that can be read at any time. Bits are cleared by writing ones to
them; writing zeros has no effect.
Table 18-1 describes SDSR Þelds.
Bits 0 1 2 3 4 5 6 7
Field SBER_P SBER_L Ñ
Reset 0000_0000
Addr 0x11018
Figure 18-3. SDMA Status Register (SDSR)
Table 18-1. SDSR Field Descriptions
Bits Name Description
0 SBER_P SDMA channel 60x bus error. Indicates that the SDMA channel on the 60x bus had terminated with
an error during a read or write transaction. This bit is cleared writing a 1; writing a zero has no effect.
The SDMA transfer error address is read from PDTEA. The channel number is read from PDTEM.
1 SBER_L SDMA channel local bus error. Indicates that the SDMA channel on the local bus had terminated with
an error during a read or write transaction. This bit is cleared writing a 1; writing a zero has no effect.
The SDMA transfer error address can be read from LDTEA, and the channel number from LDTEM.
2Ð7 Ñ Reserved, should be cleared.
CLK
TS
TA
SDMA Internally
Requests the Bus
Other Transaction SDMA Transaction Other Transaction