Processor Users Manual

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-13
Part IV. Communications Processor Module
and DMA done (DONE[1Ð4]). DREQx may also be used to control the transfer pace of
memory-to-memory transfers.
¥ DREQ
x is the external DMA request signal.
¥DACKx is the DMA acknowledge.
¥DONEx marks the end of an IDMA transfer.
The IDMA signals are multiplexed with other internal controller signals at the parallel I/O
ports. To enable the IDMA signals, the corresponding bits in the parallel I/O registers
should be set. See Chapter 35, ÒParallel I/O Ports.Ó
18.7.1 DREQx and DACKx
When the peripheral requires IDMA service, it asserts DREQx and the MPC8260 begins
the IDMA process. When the IDMA service is in progress, D
ACKx is asserted during
accesses to the peripheral. A peripheral must validate the transfer by asserting T
A or signal
an error by asserting T
EA.
DREQ
x may be conÞgured as either edge- or level-sensitive by programming the
RCCR[DRxM]. When DREQ
x is conÞgured as edge-sensitive, RCCR[EDMx] controls
whether the request is generated on the rising or falling edge; see Section 13.3.6, ÒRISC
Controller ConÞguration Register (RCCR).Ó
DREQ
x is sampled at each rising edge of the clock to determine when a valid request is
asserted by the device.
18.7.1.1 Level-Sensitive Mode
For external devices requiring very high data transfer rates, level-sensitive mode allows the
IDMA to use a maximum bandwidth to service the device. The device requests service by
asserting DREQ
x and leaving it asserted as long as it needs service. This mode is selected
by setting the corresponding RCCR[DRxM].
The IDMA asserts D
ACK each time it issues a bus transaction to either read or write the
peripheral. The peripheral must use T
A and TEA for data validation. DACK is the
acknowledgment of the original burst request given on DREQ
x. DREQx should be negated
during the D
ACK active period to ensure that no further transactions are performed.
18.7.1.2 Edge-Sensitive Mode
For external devices that generate a pulsed signal for each operand to be transferred, edge-
sensitive mode should be used. In edge-sensitive mode, the IDMA controller moves one
operand for each falling/rising (as conÞgured by RCCR[EDMx]) edge of DREQ
x. This
mode is selected by clearing the corresponding RCCR[DRxM] and programming the
corresponding RCCR[EDMx] to the proper edge.
When the IDMA controller detects a valid edge on DREQ
x, a request becomes pending and
remains pending until it is serviced by the IDMA. Subsequent changes on DREQ
x are