Processor Users Manual

19-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part IV. Communications Processor Module

Figure 19-11. CTS Lost in Synchronous Protocols

Note that if GSMR_H[CTSS] = 1, CTS transitions must occur while the Tx clock is low.

Reception delays are determined by CD

as shown in Figure 19-12. If GSMR_H[CDS] is

zero, CD

is sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS]

is 1, CD

transitions cause data to be immediately gated into the receiver.

1. GSMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur.

TCLK

TXD

First Bit of Frame Data

NOTE:

CTS Sampled Low Here

1. GSMR_H[CTSS] = 1. CTSP=0 or no CTS lost can occur.

TCLK

First Bit of Frame Data

NOTE:

CTS Sampled High Here

Data Forced High

TS Forced High

Data Forced High

TS Forced High

CTS

Lost Signaled in Frame BD

CTS

Lost Signaled in Frame BD

(Output)

CTS

(Input)

CTS

(Input)

(Output)

TXD

(Output)