Processor Users Manual

20-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 20-6 describes DSR Þelds.
20.15 Handling Errors in the SCC UART Controller
The UART controller reports character reception and transmission error conditions via the
BDs, the error counters, and the SCCE. Modem interface lines can be monitored by the port
C pins. Transmission errors are described in Table 20-7.
Table 20-6. DSR Fields Descriptions
Bit Name Description
0 Ñ 0b0
1Ð4 FSB Fractional stop bits. For 16´ oversampling:
1111 Last transmitted stop bit 16/16. Default value after reset.
1110 Last transmitted stop bit 15/16.
É
1000 Last transmitted stop bit 9/16.
0xxx Invalid. Do not use.
For 32´ oversampling:
1111 Last transmitted stop bit 32/32. Default value after reset.
1110 Last transmitted stop bit 31/32.
É
0000 Last transmitted stop bit 17/32.
For 8´ oversampling:
1111 Last transmitted stop bit 8/8. Default value after reset.
1110 Last transmitted stop bit 7/8.
1101 Last transmitted stop bit 6/8.
1100 Last transmitted stop bit 5/8.
10xx Invalid. Do not use.
0xxx Invalid. Do not use.
The UART receiver can always receive fractional stop bits. The next characterÕs start bit can begin
any time after the three middle samples have been taken.
5Ð6 Ñ 0b11
7Ð8 Ñ 0b00
9Ð14 Ñ 0b111111
15 Ñ 0b0
Table 20-7. Transmission Errors
Error Description
CTS
Lost
during
Character
Transmission
When CTS
negates during transmission, the channel stops after Þnishing the current character. The
CP sets TxBD[CT] and generates the TX interrupt if it is not masked. The channel resumes
transmission after the
RESTART TRANSMIT command is issued and CTS is asserted.
Note that if CTS
is used, the UART also offers an asynchronous ßow control option that does not
generate an error. See the description of PSMR[FLC] in Table 20-9.