Processor Users Manual

MOTOROLA Part I. Overview Part I-lxix
Part I. Overview
ISDN Integrated services digital network
ITLB Instruction translation lookaside buffer
IU Integer unit
JTAG Joint Test Action Group
LRU Least recently used (cache replacement algorithm)
LSU Load/store unit
MCC Multi-channel controller
MII Media-independent interface
MMU Memory management unit
MSR Machine state register
NMSI Nonmultiplexed serial interface
OEA Operating environment architecture
OSI Open systems interconnection
PCI Peripheral component interconnect
RISC Reduced instruction set computing
RTC Real-time clock
RTOS Real-time operating system
Rx Receive
SCC Serial communications controller
SDLC Synchronous data link control
SDMA Serial DMA
SI Serial interface
SIU System interface unit
SMC Serial management controller
SPI Serial peripheral interface
SPR Special-purpose register
SRAM Static random access memory
TAP Test access port
TB Time base register
TDM Time-division multiplexed
TLB Translation lookaside buffer
TSA Time-slot assigner
Table iv. Acronyms and Abbreviated Terms (Continued)
Term Meaning