Processor Users Manual

27-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
channels which uses the slot synchronization. Figure 27-5 shows the SI RAM
programming for the same transparent or HDLC receiver super channels that do not use slot
synchronization.
Figure 27-3. Transmitter Super Channel Example
The example in Figure 27-5 shows a receiver super channel with slot synchronization.
0 1 2 3Ð10 11Ð13 14 15
MCC LOOP SUPER MCSEL CNT BYT LST
SI RAM Address
1000x0
0x1
10
1010x1
0x0
1
1
First slot of the super channel
10
1010x2
0x0
2
10
1010x3
0x7
2
2
Regular (not Þrst) slot of the super channel
00
1010x4
0x7
2
00
1000x5
0x1
10
1010x6
0x7
2
00
1010x7
0x7
2
00
1000x8
0x1
11
0Ð1 2Ð9 10Ð15
CHANNEL NO
DPR_Base + SCTPBASE +
0x0
Ñ
0x2
0x1
0x4
0x2
0x6
0x2
0x8
0x2
0xA
Ñ
0xC
0x1
0xE
0x1
0x10
Ñ
.
The super channel BD tables are associated with channels 1 and 2 (no BD tables are necessary for
SI RAM Super Channel Table
channels 3, 4, 6, and 7)