Processor Users Manual

27-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
RSTATE high-byte Þelds are described in Table 27-6.
27.7 Channel-SpeciÞc Transparent Parameters
Table 27-7 describes channel-speciÞc parameters for transparent operation.
Bits 0 1 2 3 4 5 6 7
Field Ñ GBL BO TC2 DTB BDB
Reset Ñ
R/W R/W
Addr 0x20
Figure 27-9. Rx Internal State (RSTATE) High Byte
Table 27-6. RSTATE High-Byte Field Descriptions
Bits Name Description
0Ð1 Ñ Reserved, should be cleared.
2 GBL Global. Setting GLB activates snooping (only the 60X bus can be snooped, this parameter is ignored
for local bus transactions).
3Ð4 BO Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy,
it takes effect at the beginning of the next frame or at the beginning of the next BD.
00 Reserved
01 PowerPC little-endian.
1x Big-endian
5 TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6 DTB Data bus indicator.
The transfers to data buffers are handled by the:
0 60x bus SDMA
1 Local bus SDMA
7 BDB BD and interrupt circular tables bus indicator.
The transfers to/from BD and interrupt circular tables are handled by the:
0 60x bus SDMA
1 Local bus SDMA
Note that the following restrictions result from the fact that there is a common bus selection bit for
BDs and interrupt circular tables:
¥ The RxBDs of all the channels that use a particular interrupt table must reside on the same bus
(60x or local).
¥ All TxBDs must reside on the same bus (60x or local).
Table 27-7. Channel-Specific Parameters for Transparent Operation
Offset
1
Name Width Description
0x00 TSTATE Word Tx internal state. To start a transmitter channel the user must write to TSTATE
0xHH80_0000. HH is the TSTATE high byte described in Section 27.6.1, ÒInternal
Transmitter State (TSTATE).Ó