Processor Users Manual

28-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part IV. Communications Processor Module

Figure 28-8. CTS Lost

Note that if GFMR[CTSS] = 1, all CTS transitions must occur while the transmit clock is

low.

Reception delays are determined by CD

as Figure 28-9 shows. If GFMR[CDS] = 0, CD is

sampled on the rising receive clock edge before data is received. If GFMR[CDS] = 1, CD

transitions immediately cause data to be gated into the receiver.

1. GFMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur.

TCLK

TXD

First Bit of Frame Data

Note:

CTS Sampled Low

1. GFMR_H[CTSS] = 1. CTSP=0 or no CTS

lost can occur.

TCLK

First Bit of Frame Data

Note:

CTS Sampled High

Data Forced High

TS Forced High

Data Forced High

TS Forced High

CTS

Lost Signaled in BD

CTS

Lost Signaled in BD

(Output)

CTS

(Input)

CTS

(Input)

(Output)

TXD

(Output)