Processor Users Manual

1-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
NOTE
A bar over a signal name indicates that the signal is active
lowÑfor example, BB
(bus busy). Active-low signals are
referred to as asserted (active) when they are low and negated
when they are high. Signals that are not active low, such as
TSIZ[0Ð3] (transfer size signals) are referred to as asserted
when they are high and negated when they are low.
Figure 1-2. MPC8260 External Signals
VCCSYN/GNDSYN/VCCSYN1//VDDH/VDD/
VSS
¾¾¾>100
P
O
W
E
R
Q
U
I
C
C
II
6
0
x
B
U
S
32 <¾¾> A[0Ð31]
PAR/ L_A14 <¾¾> 1
L
O
C
A
L
B
U
S
5 <¾¾> TT[0Ð4]
SMI/FRAME/ L_A15 <¾¾> 14<¾¾> TSIZ[0Ð3]
TRDY/ L_A16 <¾¾> 11<¾¾> TBST
CKSTOP_OUT/IRDY/ L_A17 <¾¾> 11<¾¾> GBL/IRQ1
STOP/ L_A18 <¾¾> 11<¾¾> CI/BADDR29/IRQ2
DEVSEL/ L_A19 <¾¾> 11<¾¾> WT/BADDR30/IRQ3
IDSEL/ L_A20 <¾¾> 11<¾¾¾ L2_HIT/IRQ4
PERR/ L_A21 <¾¾> 11<¾¾> CPU_BG/BADDR31/IRQ5
1 ¾¾¾> CPU_DBG
1 ¾¾¾> CPU_BR
SERR/ L_A22 <¾¾> 11<¾¾> BR
REQ0/ L_A23 <¾¾> 11<¾¾> BG
REQ1/ L_A24 <¾¾> 11<¾¾> ABB/IRQ2
GNT0/ L_A25 <¾¾> 11<¾¾> TS
GNT1/ L_A26 <¾¾¾ 11<¾¾> AACK
CLK/ L_A27 <¾¾> 11<¾¾> ARTRY
CORE_SRESET/RST/ L_A28 <¾¾> 11<¾¾> DBG
INTA/ L_A29 <¾¾> 11<¾¾> DBB/IRQ3
LOCK/ L_A30 <¾¾> 164<¾¾> D[0Ð63]
L_A31 <¾¾> 11<¾¾> NC/DP0/RSRV/EXT_BR2
AD[0–31]/ LCL_D[0Ð31] <¾¾> 32 1 <¾¾> IRQ1/DP1/EXT_BG2
C/BE[0–3]/ LCL_DP[0Ð3] <¾¾> 41<¾¾> IRQ2/DP2/TLBISYNC/EXT_DBG2
LBS[0Ð3]/LSDDQM[0Ð3]/LWE[0Ð3] <¾¾¾ 4
M
E
M
C
1 <¾¾> IRQ3/DP3/CKSTP_OUT/EXT_BR3
1 <¾¾> IRQ4/DP4/CORE_SRESET/EXT_BG3
LGPL0/LSDA10 <¾¾¾ 11<¾¾> IRQ5/DP5/TBEN/EXT_DBG3
LGPL1/LSDWE <¾¾¾ 11<¾¾> IRQ6/DP6/CSE0
LGPL2/LSDRAS
/LOE <¾¾¾ 11<¾¾> IRQ7/DP7/CSE1
LGPL3/LSDCAS <¾¾¾ 11<¾¾> PSDVAL
LPBS/LGPL4/LUPWAIT/LGTA <¾¾> 11<¾¾> TA
LGPL5 <¾¾> 11<¾¾> TEA
LWR <¾¾> 11<¾¾> IRQ0/NMI_OUT
PA[0Ð31] <¾¾> 32
P
I
O
1 <¾¾> IRQ7/INT_OUT/APE
PB[4Ð31] <¾¾> 28
M
E
M
C
10 ¾¾¾> CS[0Ð9]
PC[0Ð31] <¾¾> 32 1 <¾¾> CS[10]/BCTL1/DBG_DIS
PD[4Ð31] <¾¾> 28 1 <¾¾> CS
[11]/AP[0]
PORESET¾¾¾> 1
R
S
T
C
L
K
2 ¾¾¾> BADDR[27Ð28]
RSTCONF¾¾¾> 11¾¾¾> ALE
HRESET<¾¾> 11¾¾¾> BCTL0
SRESET<¾¾> 18¾¾¾> PWE[0Ð7]/PSDDQM[0Ð7]/PBS[0Ð7]
QREQ<¾¾¾ 11¾¾¾> PSDA10/PGPL0
1 ¾¾¾> PSDWE/PGPL1
XFC¾¾¾> 11¾¾¾> POE/PSDRAS/PGPL2
1 ¾¾¾> PSDCAS
/PGPL3
CLKIN¾¾¾> 11<¾¾> PGTA/PUPMWAIT/PGPL4/PPBS
TRIS¾¾¾> 11¾¾¾> PSDAMUX/PGPL5
BNKSEL[0]/TC[0]/AP[1]/MODCK1<¾¾> 1
J
T
A
G
1 <¾¾- TMS
BNKSEL[1]/TC[1]/AP[2]/MODCK2
<¾¾> 11<¾¾¾TDI
BNKSEL[2]/TC[2]/AP[3]/MODCK3<¾¾> 11<¾¾- TCK
TERM[0Ð1] ¾¾¾> 21<¾¾- TRST
NC ¾¾¾> 41-¾¾> TDO