Processor Users Manual

29-57 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
29.10.2.3.5 UBR+ Protocol-SpeciÞc TCTE
Figure 29-35 shows the UBR+ protocol-speciÞc TCTE.
Table 29-26 describes UBR+ protocol-speciÞc TCTE Þelds.
0x06 0Ð7 SRR Sustain rate remainder. Holds the sustain rate remainder after adding the pace fraction Þeld
to the additive channel sustain rate. Used by the APC to calculate the channel GCRA (leaky
bucket) state. Initialized to 0.
8Ð15 SCRF Holds the sustain cell rate fraction of this channel in units of 1/256 slot.
0x08 Ñ SR Sustain rate. Used by the APC to hold the sustain rate after adding the pace Þeld to the
additive channel sustain rate. Used by the APC to calculate the channel GCRA (leaky
bucket) state.
0x0C 0 VBR2 VBR type
0 Regular VBR. CLP=0+1 cells are rescheduled by PCR or SCR according to the GCRA
state.
1 VBR Type 2. CLP=0 cells are rescheduled by PCR or SCR according to the GCRA state.
CLP=1 cells are rescheduled by PCR.
1Ð15 Ñ Reserved, should be cleared.
0x0EÐ
0x1E
Ñ Ñ Reserved, should be cleared.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0x00 MCR
Offset + 0x02 Ñ MCR Fraction (MCRF)
Offset + 0x04 Maximum Delay Allowed (MDA)
Offset + 0x06Ð0x1E Ñ
Figure 29-35. UBR+ Protocol-Specific TCTE
Table 29-26. UBR+ Protocol-Specific TCTE Field Descriptions
Offset Bits Name Description
0x00 Ñ MCR Minimum cell rate for this channel. MCR is in units of APC time slots.
0x02 0Ð7 Ñ Reserved, should be cleared.
8Ð
15
MCRF Minimum cell rate fraction. Holds the minimum cell rate fraction of this channel in units of 1/
256 slot.
0x04 Ñ MDA Maximum delay allowed. The maximum time-slot service delay allowed for this priority level
before the APC reduces the scheduling rate from PCR to MCR.
0x06Ð
0x1E
Ñ Ñ Reserved, should be cleared.
Table 29-25. VBR-Specific TCTE Field Descriptions (Continued)
Offset Bits Name Description