Processor Users Manual

MOTOROLA Chapter 31. FCC HDLC Controller 31-15
Part IV. Communications Processor Module
Figure 31-8 shows interrupts that can be generated in the HDLC protocol.
Table 31-9. FCCE/FCCM Field Descriptions
Bits Name Description
0Ð7 Ñ Reserved, should be cleared.
8 GRA Graceful stop complete. A graceful stop, which was initiated by the
GRACEFUL STOP TRANSMIT
command, is now complete. GRA is set as soon as the transmitter Þnishes transmitting any frame
that is in progress when the command was issued. It is set immediately if no frame is in progress
when the command is issued.
9Ð10 Ñ Reserved, should be cleared.
11 TXE Tx error. An error (CTS
lost or underrun) occurs on the transmitter channel.
12 RXF Rx frame. A complete frame is received on the HDLC channel. This bit is set no sooner than two
clocks after receipt of the last bit of the closing ßag.
13 BSY Busy condition. A frame is received and discarded due to a lack of buffers.
14 TXB Transmit buffer. A buffer is sent on the HDLC channel. TXB is set no sooner than when the last bit
of the closing ßag begins its transmission if the buffer is the last one in the frame. Otherwise, TXB
is set after the last byte of the buffer is written to the transmit FIFO buffer.
15 RXB Receive buffer. A buffer that is not a complete frame is received on the HDLC channel.
16Ð21 Ñ Reserved, should be cleared.
22 FLG Flag status changed. The HDLC controller stops or starts receiving HDLC ßags. The real-time
status can be obtained in FCCS; see Section 31.10, ÒFCC Status Register (FCCS).Ó
23 IDL Idle sequence status changed. A change in the status of the serial line is detected on the HDLC
line. The real-time status can be read in FCCS; see Section 31.10, ÒFCC Status Register (FCCS).Ó
24Ð31 Ñ Reserved, should be cleared.