Processor Users Manual

MOTOROLA Index Index-11
INDEX
IDSR (IDMA event (status) register), 18-22
IEEE 1149.1 test access port
block diagram, 12-2
boundary scan register, 12-3
instruction decoding, 12-29
instruction register, 12-28
nonscan chain operation, 12-30
overview, 12-1
restrictions, 12-30
TAP controller, 12-2
IMMR (internal memory map register), 4-34
Input/output port memory map, 3-5
Instruction field conventions, lxv
Instruction timing overview, 2-29
Instruction unit, 2-5
Integer unit overview, 2-6
Interrupts
ATM interrupt queues, 29-79
RISC timer tables
interrupt handling, 13-23
SCC interrupt handling, 19-16
J
JTAG implementation, 12-28
L
L_TESCR1 (local bus transfer error status and control
register 1), 4-38
L_TESCR2 (local bus transfer error status and control
register 2), 4-39
L_TESCRx (local bus error status and control
registers), 10-33
LCL_ACR (local bus arbiter configuration
register), 4-29
LCL_ALRH (local bus arbitration high-level
register), 4-30
LCL_ALRL (local bus arbitration low-level
register), 4-30
LDTEA (SDMA local bus transfer error address
register), 18-4
LDTEM (SDMA local bus transfer error MSNUM
register), 18-4
Loopback mode, 14-7
LSDMR (local bus SDRAM mode register), 10-24
LSRT (local bus-assigned SDRAM refresh timer)
register, 10-32
LURT (local bus-assigned UPM refresh timer)
register, 10-30
M
MCCE (MCC event) register, 27-18
MCCFx (MCC configuration registers), 27-15
MCCM (MCC mask) register, 27-18
MDR (memory data register), 10-28
Memory controller
address checking, 10-8
address latch enable (ALE), 10-11
address space checking, 10-8
architecture overview, 10-5
atomic bus operation, 10-10, 10-10
basic architecture, 10-5
basic operation, 10-8
boot chip-select operation, 10-61
controlling the timing of GPL1
, GPL2, and
CSx
, 10-68
CSx timing example, 10-68
delayed read, 10-10
EDO interface connection, MPC8260 to
60x bus, 10-92
error checking and correction (ECC), 10-9
external master support, 10-101
external support, 10-11
features common to all machines, 10-6
features list, 10-3
general-purpose chip-select machine (GPCM)
access termination, external, 10-60
assertion timing, 10-53
common features, 10-6
differences between MPC8xx and
MPC8260, 10-62
external access termination, 10-60
implementation differences with UPMs
and SDRAM machine, 10-7
interface signals, 10-51
MPC8xx versus MPC8260, 10-62
OE timing, 10-57, 10-57
overview, 10-51
programmable wait state
configuration, 10-57
PSDVAL, 10-57
read access extended hold time, 10-57
relaxed timing, 10-55
SRAM configuration, 10-51
strobe signal behavior, 10-52
terminating external accesses, 10-60
timing configuration, 10-52, 10-52
write enable deassertion timing, 10-54
GPLn timing example, 10-68
implementation differences between
machines, 10-7
machine selection, 10-6
MAR in 60x-compatible mode, 10-77
new features supported, 10-2
overview, 10-1
page hit checking, 10-9
parity byte select (PBSE), 10-11
parity checking, 10-9
parity generation, 10-9