User`s guide

MPC8240 and MPC8260 Emulation 137
Chapter 10: Troubleshooting the Emulator
Problems with the Target System
2 Hand load a little program:
start: addi r1,1 - 0x38210001
nop - 0x60000000
nop - 0x60000000
bra start - 0x4bfffff4
The opcode 0x4bfffff4 is a branch to a relative offset, so this program
can be placed at any start address.
M>reg r1=0
M>m -a2 -d2 10000=3821,1,6000,0,6000,0,4bff,fff4
M>r 10000
U>reg r1
reg r1=00034567 # or some number
U>reg r1
reg r1=00102333 # or some number
U>
This program will loop forever, incrementing r1. This is a good test
program to load once a memory system is up to make sure the
microprocessor can run code out of memory.
If running from reset causes problems
Running from reset may cause some problems once background is
entered. To ensure proper operation, the DER register must have bits
31,30,29,28 set (0x0000000f), and the SYPCR register must have the
’Disable watchdog freeze’ bit set (0x00000080).
If you see the "!ASYNC_STAT 173!" error
message
If after a break, the following error arises:
!ASYNC_STAT 173! MSR.RI bit not set - Break may not be
recoverable
This indicates that the MSR.RI bit is not set, implying that a non-
maskable break was needed, and the interrupt may not be recoverable.
If this occurs while breaking out of regular code, then the MSR.RI bit