MVME166 Single Board Computer Installation Guide (MVME166IG/D2)
Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Preface This manual provides general board level hardware description, hardware preparation and installation instructions, debugger general information, and using the debugger; for the MVME166 Single Board Computer. This manual is intended for anyone who wants to provide OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes. A basic knowledge of computers, and digital logic is assumed.
The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., first published 1990, and may be used only under a license such as the License for Computer Programs (Article 14) contained in Motorola’s Terms and Conditions of Sale, Rev. 1/79. ! WARNING This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in accordance with the documentation for this product, may cause interference to radio communications.
Safety Summary Safety Depends On You The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer’s failure to comply with these requirements.
Use Caution When Exposing or Handling the CRT. Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only by qualified maintenance personnel using approved safety mask and gloves. Do Not Substitute Parts or Modify Equipment.
Contents CHAPTER 1 BOARD LEVEL HARDWARE DESCRIPTION Introduction .............................................................................................................1-1 Overview...........................................................................................................1-1 Related Documentation ..................................................................................1-2 Requirements.............................................................................................
VMEbus Accesses to the Local Bus...................................................... 1-22 VMEbus Short I/O Memory Map............................................................1-22 VSB Memory Map .............................................................................................1-22 CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION Introduction .................................................................................................................2-1 Unpacking Instructions.............
Device Probe Function ..................................................................................... 3-16 Disk I/O via 166Bug Commands ................................................................... 3-16 IOI (Input/Output Inquiry) ..................................................................... 3-16 IOP (Physical I/O to Disk) ....................................................................... 3-16 IOT (I/O Teach) ...........................................................................
166Bug Generalized Exception Handler .................................................4-15 Floating Point Support.............................................................................................4-17 Single Precision Real .........................................................................................4-18 Double Precision Real .......................................................................................4-18 Extended Precision Real ...............................................
List of Figures FIGURES Figure 1-1. MVME166 Block Diagram..................................................................1-8 Figure 2-1. MVME166 Switches, Headers, Connectors, Fuses, and LEDs ......
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List of Tables TABLES Table 1-1. MVME166 Specifications......................................................................1-6 Table 1-2. Local Bus Memory Map .....................................................................1-19 Table 1-3. Local I/O Devices Memory Map ......................................................1-20 Table 4-1. Debugger Address Parameter Formats..............................................4-5 Table 4-2. Exception Vectors Used by 166Bug........................................
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BOARD LEVEL HARDWARE DESCRIPTION 1 Introduction This chapter describes the board level hardware features of the MVME166 Single Board Computers. The chapter is organized with a board level overview and features list in this introduction, followed by a more detailed hardware functional description. Front panel switches and indicators are included in the detailed hardware functional description. The chapter closes with some general memory maps.
1 Board Level Hardware Description Processor-to-VMEbus transfers can be D8, D16, or D32. VMEchip2 DMA transfers to the VMEbus, however, can be D16, D32, D16/BLT, D32/BLT, or D64/MBLT. The VSBchip2 provides the VSB interface on the MVME166. The VSBchip2 includes programmable map decoders for the master and slave interfaces, a VSB master interface, a VSB slave interface, a VSB interrupter, a VSB interrupt handler, a VSB serial requester, a VSB serial arbiter, and a VSB parallel requester.
Introduction Document Title Motorola Publication Number Single Board Computers SCSI Software User’s Manual SBCSCSI MVME166/MVME167/MVME187 Single Board Computers Programmer’s Reference Guide MVME187PG MVME712-06/07/09 I/O Distribution Board Set User’s Manual MVME712IO MVME712-10 Transition Module User’s Manual MVME712-10 M68040 Microprocessors User’s Manual M68040UM N otes The SIMVME166 manual contains: the connector interconnect signal information, parts lists, and the schematics; for the MVM
1 Board Level Hardware Description To further assist your development effort, Motorola has collected user’s manuals for each of the peripheral controllers used on the MVME166 from the suppliers.
Introduction Requirements These boards are designed to conform to the requirements of the following documents: ❏ ❏ ❏ ❏ VMEbus Specification (IEEE 1014-87) EIA-232-D Serial Interface Specification, EIA SCSI Specification, ANSI VSB Specification (IEEE 1096-1988) Features Features of the MVME166 are listed below.
1 Board Level Hardware Description Specifications General specifications for the MVME166 are listed in Table 1-1. Table 1-1. MVME166 Specifications Characteristics Specifications Power requirements (excluding external LAN transceiver) (at 33 MHz with 32 MB ECC memory) +5 Vdc (± 5%), 5.0 A (typical), 6.5 A (max.) (includes transition modules) +12 Vdc (± 5%), 100 mA (max.) (1.0 A (max.) with offboard LAN transceiver) -12 Vdc (± 5%), 100 mA (max.
Introduction An asterisk (*) following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition. In this manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent.
1 Board Level Hardware Description Block Diagram Figure 1-1 is a general block diagram of the MVME166. MC68040 DRAM 82596CA LAN ETHERNET VMEchip2 VMEbus 53C710 SCSI FLASH MK48T08 BBRAM & CLOCK CD2401 SCC SERIAL IO PRINTER PORT PCCchip2 DOWNLOAD EPROM VSBchip2 128KB STATIC RAM VSB bd078 9304 Figure 1-1.
Functional Description Functional Description This section contains a functional description of the major blocks on the MVME166 Single Board Computers. Front Panel Switches and Indicators There are switches and LEDs on the front panel of the MVME166. The switches are RESET and ABORT. The RESET switch resets all onboard devices and drives SYSRESET* if the board is system controller. The RESET switch may be disabled by software.
1 Board Level Hardware Description Data Bus Structure The local data bus on the MVME166 is a 32-bit synchronous bus that is based on the MC68040 bus, and supports burst transfers and snooping. The various local bus master and slave devices use the local bus to communicate. The local bus is arbitrated by priority type arbiter and the priority of the local bus masters from highest to lowest is: 82596CA LAN, CD2401 serial (through the PCCchip2), 53C710 SCSI, VSB, VMEbus, and MPU.
Functional Description Before you perform any SCSI, VMEbus, or Ethernet I/O with the MVME166, it may be necessary to define some parameters (e.g., SCSI ID, Ethernet address, VMEbus mapping). For details on configuring the MVME166, refer to the setup command description in Chapter 3 in this manual, and in the MVME167Bug Debugging Package User’s Manual. SRAM The boards include 128KB of 32-bit wide static RAM with onboard battery backup that supports 8-, 16-, and 32-bit wide accesses.
1 Board Level Hardware Description with the board powered off and the board at 40° C. If the power-on duty cycle is 50% (the board is powered on half of the time), the battery lifetime is four years. At lower ambient temperatures the backup time is greatly extended and may approach the shelf life of the battery. When a board is stored, the battery should be disconnected to prolong battery life. This is especially important at high ambient temperatures.
Functional Description The DRAM map decoder can be programmed to accommodate different base address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed. Refer to the MCECC in the MVME166/MVME167/MVME187 Single Board Computers Programmer’s Reference Guide for detailed programming information. Most DRAM devices require some number of access cycles before the DRAMs are fully operational.
1 Board Level Hardware Description at synchronous bit rates up to 64 k bits per second. They use RXD, CTS, DCD, TXD, RTS, DTR, and DSR. They also interface to the synchronous clock signal lines. Additional control signals are provided for each serial port by the MC68230. These include local loopback control, self test control, and ring indicator. The ring indicator signal can be programmed to generate a local bus interrupt. Refer to the MC68230 section for additional information.
Functional Description The presence of the MC68230 can be determined by reading address $FFF45C00. If a timeout error occurs, then the board is an MVME166 and and the MC68230 is present. If a timeout does not occur, then the board is an MVME167/187 and the MC68230 is not present. The local bus timeout timer in the VMEchip2 must be enabled for this test. The MC68230 may be used for general purpose I/O when the MVME166 is not used with the MVME712 family of transition modules.
1 Board Level Hardware Description Every MVME166 is assigned an Ethernet Station Address. The address is $08003E2XXXXX where XXXXX is the unique 5-nibble number assigned to the board (i.e., every MVME166 has a different value for XXXXX). Each module has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector. In addition, the six bytes including the Ethernet address are stored in the configuration area of the BBRAM. That is, 08003E2XXXXX is stored in the BBRAM.
Functional Description Programmable Tick Timers Four 32-bit programmable tick timers with 1 µs resolution are provided, two in the VMEchip2 and two in the PCCchip2. The tick timers can be programmed to generate periodic interrupts to the processor. Watchdog Timer A watchdog timer function is provided in the VMEchip2. When the watchdog timer is enabled, it must be reset by software within the programmed time or it times out.
1 Board Level Hardware Description Memory Maps There are two points of view for memory maps: 1) the mapping of all resources as viewed by local bus masters (local bus memory map), 2) the mapping of onboard resources as viewed by externa masters (VMEbus memory map or VSB memory map). Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes.
Memory Maps Table 1-2.
1 Board Level Hardware Description The following table focuses on the Local I/O Devices portion of the local bus Main Memory Map. Table 1-3. Local I/O Devices Memory Map Address Range Devices Accessed Port Size Size Notes 256KB 5 D32 256B 1,4 D32-D8 256B 1,4 reserved -- 3.
Memory Maps 2. On the MVME166 this area does not return an acknowledge signal. If the local bus timer on the MVME166 is enabled, the access times out and is terminated by a TEA signal. On the MVME187 this area is used. 3. Byte reads should be used to read the interrupt vector. These locations do not respond when an interrupt is not pending. If the local bus timer is enabled, the access times out and is terminated by a TEA signal. 4. Writes to the LCSR in the VMEchip2 must be 32 bits.
1 Board Level Hardware Description VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters. Default addresses for the slave, master, and GCSR address decoders are provided by the ENV command. Refer to Appendix A. VMEbus Accesses to the Local Bus The VMEchip2 includes a user-programmable map decoder for the VMEbus to local bus interface. The map decoder allows you to program the starting and ending address and the modifiers the MVME166 responds to.
HARDWARE PREPARATION AND INSTALLATION 2 Introduction This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MVME166. Hardware preparation and installation for the MVME712 series transition modules is described in a separate manual. Refer to the Related Documentation section in Chapter 1. Unpacking Instructions N ote If the shipping carton is damaged upon receipt, request carrier’s agent be present during unpacking and inspection of equipment.
Hardware Preparation and Installation Figure 2-1 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME166. The MVME166 has been factory tested and is shipped with the factory jumper settings described in the following sections. The MVME166 operates with its required and factoryinstalled Debug Monitor, MVME166Bug (166Bug), with these factory jumper settings.
Hardware Preparation 2 MVME 166 LGA A1 B1 C1 FAIL STAT DS1 RUN SCON DS2 LAN RPWR DS3 SCSI VME DS4 1 TPWR VSB J2 DS5 P1 2 ABORT 1 J3 15 F1 S1 RESET 2 16 1 2 S2 J6 5 1 F2 J7 34 33 68 67 A32 B32 C32 2 6 F3 J8 F4 2 1 36 35 PRIMARY SIDE SCSI A1 B1 C1 MEZZANINE BOARD 49 50 99 100 J9 P2 I/O A32 B32 C32 1 2 51 22 1381 9404 Figure 2-1.
Hardware Preparation and Installation 2 General Purpose Readable Jumpers on Header J3 Each MVME166 may be configured with readable jumpers. These jumpers can be read as a register (at $FFF40088) in the VMEchip2 LCSR. The bit values are read as a one when the jumper is off, and as a zero when the jumper is on.
Hardware Preparation SRAM Backup Power Source Select Header J7 2 Header J7 is used to select the power source used to backup the SRAM on the MVME166.
Hardware Preparation and Installation 2 Installation Instructions The following sections discuss the installation of the MVME166 in a VME chassis, and describe system considerations relevant to the installation. Ensure that an EPROM device is installed as needed. The factory configuration provides for one EPROM (installed for 166BBug, the BootBug firmware subset of the MVME166Bug debug monitor contained in Flash memory) in socket U12. Ensure that all header jumpers are configured as desired.
Installation Instructions The MVME166 is to be installed in the front of the chassis. The MVME712 module(s) is/are to be installed either in the front or the rear of the chassis, depending on the I/O option you select: Through the front panel I/O connector via cable to the MVME712-10 transition module, which may be mounted either in the forward card cage alongside the MVME166 (recommended) or in the rear transition module area.
Hardware Preparation and Installation h. Replace the chassis cover. 2 i. Connect the power cable to the ac power source and turn the equipment power ON. System Considerations The MVME166 draws power from both the P1 and P2 connectors on the VMEbus backplane. P2 is also used for the upper 16 bits of data for 32-bit transfers, and for the upper 8 address lines for extended addressing mode. The MVME166 may not operate properly without its main board connected to P1 and P2 of the VMEbus backplane.
Installation Instructions Other MPUs on the VMEbus can interrupt, disable, communicate with and determine the operational status of the processor(s). One register of the GCSR set includes four bits which function as location monitors to allow one MVME166 processor to broadcast a signal to other MVME166 processors, if any are present. All eight registers are accessible from any local processor as well as from the VMEbus.
Hardware Preparation and Installation 2 2-10 MVME166 Single Board Computer Installation Guide
DEBUGGER GENERAL INFORMATION 3 Overview of M68000 Firmware The firmware for the M68000-based (68K) series of board and system level products has a common genealogy, deriving from the BUG firmware currently used on all Motorola M68000-based CPU modules. The M68000 firmware family provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance.
Debugger General Information When using 166Bug, you operate out of either the debugger directory or the diagnostic directory. If you are in the debugger directory, the debugger prompt "166-Bug>" is displayed and you have all of the debugger commands at your disposal. If you are in the diagnostic directory, the diagnostic prompt "166-Diag>" is displayed and you have all of the diagnostic commands at your disposal as well as all of the debugger commands.
166Bug Implementation 166Bug Implementation MVME166Bug is written largely in the "C" programming language, providing benefits of portability and maintainability. Where necessary, assembler has been used in the form of separately compiled modules containing only assembler code - no mixed language modules are used. Physically, 166Bug is contained in four Flash memory components. The onboard Flash memory provides 1.0MB (256KB longwords) of nonvolatile storage.
Debugger General Information C aution 3 1. Inserting or removing modules while power is applied could damage module components. Turn all equipment power OFF. Refer to the Hardware Preparation section in Chapter 2 and install/remove jumpers on headers as required for your particular application. Jumpers on header J3 affect 166Bug operation as listed below. The default condition is with all eight jumpers installed, between pins 1-2, 3-4, 5-6, 7-8, 9-10, 11-12, 13-14, and 15-16.
Installation and Startup Bit J3 Pins Description Bit #0 (GPI0) 1-2 When this bit is a one (high), it instructs the debugger to use local Static RAM for its work page (i.e., variables, stack, vector tables, etc.). Bit #1 (GPI1) 3-4 When this bit is a one (high), it instructs the debugger to use the default setup/operation parameters in ROM versus the user setup/operation parameters in NVRAM. This is the same as depressing the RESET and ABORT switches at the same time.
Debugger General Information 3. Refer to the set-up procedure for your particular chassis or system for details concerning the installation of the MVME166. 4. Connect the terminal which is to be used as the 166Bug system console to the default debug EIA-232-D port at serial port 1 on front panel I/O connector J9 through an MVME712-10 or MVME712-06 transition module. Refer to the MVME166/MVME167/MVME187 Single Board Computers Programmer’s Reference Guide for some possible connection diagrams.
BOOTBUG 6. Power up the system. 166Bug executes some self-checks and displays the debugger prompt "166-Bug>" (if 166Bug is in Board Mode). However, if the ENV command (Appendix A) has put 166Bug in System Mode, the system performs a selftest and tries to autoboot. Refer to the ENV and MENU commands. They are listed in Table 4-3. If the confidence test fails, the test is aborted when the first fault is encountered. If possible, an appropriate message is displayed, and control then returns to the menu.
Debugger General Information Execute User Program EXEC [ADDR] The EXEC command is used to initiate target code execution. The specified address ("ADDR") is placed in the target Program Counter (PC). Execution will start at the target PC address. 3 Setup System Parameters SETUP Setup allows configuring certain parameters that are necessary for some I/O operations (SCSI, VME, and Ethernet).
Autoboot Autoboot Autoboot is a software routine that is contained in the 166Bug Flash /ROM firmware to provide an independent mechanism for booting an operating system. This autoboot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted. If a valid bootable device is found, a boot from that device is started.
Debugger General Information ROMboot On the MVME166, if you want to add other firmware applications, you must note that anytime Flash memory is programmed, the entire contents of Flash will be erased, including the 166Bug product! You should make use of the "block move" command (BM) to copy the debugger from Flash to RAM, combine your own object with the debugger in RAM, and then reprogram Flash from this combined image.
Restarting the System controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highest LUN detected. (Refer to Appendix C for default LUNs.) At power-up, Network Boot is enabled, and providing the drive and controller numbers encountered are valid, the following message is displayed upon the system console: "Network Boot in progress... To abort hit " Following this message there is a delay to allow you to abort the Auto Boot process if you wish.
Debugger General Information registers are invalidated. Input and output character queues are cleared. Onboard devices (timer, serial ports, etc.) are reset, and the first two serial ports are reconfigured to their default state. During WARM reset, the 166Bug variables and tables are preserved, as well as the target state registers and breakpoints. 3 Reset must be used if the processor ever halts, or if the 166Bug environment is ever lost (vector table is destroyed, stack corrupted, etc.).
Memory Requirements ❏ confidence test failure ❏ NVRAM checksum error ❏ NVRAM low battery condition ❏ local memory configuration status ❏ self test (if system mode) has completed with error ❏ MPU clock speed calculation failure 3 After debugger initialization is done and none of the above situations have occurred, the SYSFAIL* line is negated. This indicates to the user or VMEbus masters the state of the debugger.
Debugger General Information Terminal Input/Output Control When entering a command at the prompt, the following control codes may be entered for limited command line editing. 3 N ote 3-14 The presence of the caret ( ^ ) before a character indicates that the Control (CTRL) key must be held down while striking the character key. ^X (cancel line) The cursor is backspaced to the beginning of the line.
Disk I/O Support When observing output from any 166Bug command, the XON and XOFF characters which are in effect for the terminal port may be entered to control the output, if the XON/XOFF protocol is enabled (default). These characters are initialized to ^S and ^Q respectively by 166Bug, but you may change them with the PF command. In the initialized (default) mode, operation is as follows: ^S (wait) Console output is halted. ^Q (resume) Console output is resumed.
Debugger General Information Device Probe Function A device probe with entry into the device descriptor table is done whenever a specified device is accessed; i.e., when system calls .DSKRD, .DSKWR, .DSKCFIG, .DSKFMT, and .DSKCTRL, and debugger commands BH, BO, IOC, IOP, IOT, MAR, and MAW are used. 3 The device probe mechanism utilizes the SCSI commands "Inquiry" and "Mode Sense". If the specified controller is non-SCSI, the probe simply returns a status of "device present and unknown".
Disk I/O Support IOC (I/O Control) IOC allows you to send command packets as defined by the particular controller directly. IOC can also be used to look at the resultant device packet after using the IOP command. BO (Bootstrap Operating System) BO reads an operating system or control program from the specified device into memory, and then transfers control to it. BH (Bootstrap and Halt) BH reads an operating system or control program from a specified device into memory, and then returns control to 166Bug.
Debugger General Information To perform a disk operation, 166Bug must eventually present a particular disk controller module with a controller command packet which has been especially prepared for that type of controller module. (This is accomplished in the respective controller driver module.) A command packet for one type of controller module usually does not have the same format as a command packet for a different type of module.
Network I/O Support Disk I/O Error Codes 166Bug returns an error code if an attempted disk operation is unsuccessful. Network I/O Support 3 The Network Boot Firmware provides the capability to boot the CPU through the ROM debugger using a network (local Ethernet interface) as the boot device. The booting process is executed in two distinct phases. ❏ The first phase allows the diskless remote node to discover its network identify and the name of the file to be booted.
Debugger General Information RARP/ARP Protocol Modules The Reverse Address Resolution Protocol (RARP) basically consists of an identity-less node broadcasting a "whoami" packet onto the Ethernet, and waiting for an answer. The RARP server fills an Ethernet reply packet up with the target’s Internet Address and sends it. 3 The Address Resolution Protocol (ARP) basically provides a method of converting protocol addresses (e.g., IP addresses) to local area network addresses (e.g., Ethernet addresses).
Multiprocessor Support Multiprocessor Support The MVME166 dual-port RAM feature makes the shared RAM available to remote processors as well as to the local processor. This can be done by either of the following two methods. Either method can be enabled/disabled by the ENV command as its Remote Start Switch Method (refer to Appendix A).
Debugger General Information The Multiprocessor Address Register (MPAR), located in shared RAM location of $804 offset from the base address the debugger loads it at, contains the second of two longwords used to control communication between processors. The MPAR contents specify the address at which execution for the remote processor is to begin if the MPCR contains a G or B.
Diagnostic Facilities GCSR Method A remote processor can initiate program execution in the local MVME166 dual-port RAM by issuing a remote GO command using the VMEchip2 Global Control and Status Registers (GCSR). The remote processor places the MVME166 execution address in general purpose registers 0 and 1 (GPCSR0 and GPCSR1). The remote processor then sets bit 8 (SIG0) of the VMEchip2 LM/SIG register. This causes the MVME166 to install breakpoints and begin execution.
Debugger General Information 3 3-24 MVME166 Single Board Computer Installation Guide
USING THE 166Bug DEBUGGER 4 Entering Debugger Command Lines 166Bug is command-driven and performs its various operations in response to user commands entered at the keyboard. When the debugger prompt (166-Bug>) appears on the terminal screen, then the debugger is ready to accept commands. As the command line is entered, it is stored in an internal buffer.
Using the 166Bug Debugger The commands are shown using a modified Backus-Naur form syntax. The metasymbols used are: 4 boldface strings A boldface string is a literal such as a command or a program name, and is to be typed just as it appears. italic strings An italic string is a "syntactic variable" and is to be replaced by one of a class of items it represents.
Entering Debugger Command Lines Expression as a Parameter An expression can be one or more numeric values separated by the arithmetic operators: plus (+), minus (-), multiplied by (*), divided by (/), logical AND (&), shift left (<<), or shift right (>>). Numeric values may be expressed in either hexadecimal, decimal, octal, or binary by immediately preceding them with the proper base identifier.
Using the 166Bug Debugger Valid expression examples: Expression 4 Result (In Hex) FF0011 FF0011 45+99 DE &45+&99 90 Notes @35+@67+@10 5C %10011110+%1001 A7 88<<4 880 shift left AA&F0 A0 logical AND The total value of the expression must be between 0 and $FFFFFFFF. Address as a Parameter Many commands use ADDR as a parameter. The syntax accepted by 166Bug is similar to the one accepted by the MC68040 one-line assembler. All control addressing modes are allowed.
Entering Debugger Command Lines Table 4-1. Debugger Address Parameter Formats Format Example Description N 140 Absolute address+contents of automatic offset register. N+Rn 130+R5 Absolute address+contents of the specified offset register (not an assembler-accepted syntax). (An) (A1) Address register indirect. (also postincrement, predecrement) (d,An) or d(An) (120,A1) 120(A1) Address register indirect with displacement (two formats accepted).
Using the 166Bug Debugger N ote In commands with RANGE specified as ADDR DEL ADDR, and with size option W or L chosen, data at the second (ending) address is acted on only if the second address is a proper boundary for a word or longword, respectively. Offset Registers 4 Eight pseudo-registers (R0 through R7) called offset registers are used to simplify the debugging of relocatable and position-independent modules.
Entering Debugger Command Lines Example: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ****** ****** A portion of the listing file of an assembled, relocatable module is shown below: 0 0 0 0 0 0 0 0 00000000 00000004 00000006 00000008 0000000A 0000000C 00000010 00000014 48E78080 4280 1018 5340 12D8 51C8FFFC 4CDF0101 4E75 * * MOVE STRING SUBROUTINE * MOVESTR MOVEM.L D0/A0,—(A7) CLR.L D0 MOVE.B (A0)+,D0 SUBQ.W #1,D0 LOOP MOVE.B (A0)+,(A1)+ MOVS DBRA D0,LOOP MOVEM.
Using the 166Bug Debugger By using one of the offset registers, the disassembled code addresses can be made to match the listing file addresses as follows: 166Bug>OF R0 R0 =00000000 00000000? 1327C. 166Bug>MD 0+R0;DI 00000+R0 48E78080 00004+R0 4280 00006+R0 1018 00008+R0 5340 0000A+R0 12D8 0000C+R0 51C8FFFC 00010+R0 4CDF0101 00014+R0 4E75 166Bug> 4 MOVEM.L CLR.L MOVE.B SUBQ.W MOVE.B DBF MOVEM.
Entering and Debugging Programs Entering and Debugging Programs There are various ways to enter a user program into system memory for execution. One way is to create the program using the Memory Modify (MM) command with the assembler/disassembler option. You enter the program one source line at a time. After each source line is entered, it is assembled and the object code is loaded to memory.
Using the 166Bug Debugger If your application enables translation through the Memory Management Units (MMUs), and if your application utilizes resources of the debugger (e.g., system calls), your application must create the necessary translation tables for the debugger to have access to its various resources. The debugger honors the enabling of the MMUs; it does not disable translation.
Preserving the Debugger Operating Environment Exception Vectors Used by 166Bug The exception vectors used by the debugger are listed below. These vectors must reside at the specified offsets in the target program’s vector table for the associated debugger facilities (breakpoints, trace mode, etc) to operate. Table 4-2.
Using the 166Bug Debugger Example: Trace one instruction using debugger. 166Bug>RD PC =00010000 SR =2700=TR:OFF_S._7_..... USP =0000DFFC MSP =0000EFFC ISP* =0000FFFC DFC =0=F0 CACR =0=........ D0 =00000000 D1 =00000000 D2 =00000000 D4 =00000000 D5 =00000000 D6 =00000000 A0 =00000000 A1 =00000000 A2 =00000000 A4 =00000000 A5 =00000000 A6 =00000000 00010000 203C0000 0001 MOVE.L #$1,D0 166Bug>T PC =00010006 SR =2700=TR:OFF_S._7_..... USP =0000DFFC MSP =0000EFFC ISP* =0000FFFC DFC =0=F0 CACR =0=........
Preserving the Debugger Operating Environment The 166Bug initializes the target vector table with the debugger vectors listed in Table 4-2 and fills the other vector locations with the address of a generalized exception handler (refer to the 166Bug Generalized Exception Handler section in this chapter). The target program may take over as many vectors as desired by simply writing its own exception vectors into the table.
Using the 166Bug Debugger The following is an example of a routine which builds a separate vector table and then moves the VBR to point at it: * *** BUILDX - Build exception vector table **** * BUILDX MOVEC.L VBR,A0 Get copy of VBR. LEA $10000,A1 New vectors at $10000. MOVE.L $80(A0),D0 Get generalized exception vector. MOVE.W $3FC,D1 Load count (all vectors). LOOP MOVE.L D0,(A1,D1) Store generalized exception vector. SUBQ.W #4,D1 BNE.B LOOP Initialize entire vector table. MOVE.
Preserving the Debugger Operating Environment The following is an example of an exception handler which can pass an exception along to the debugger: * *** EXCEPT - Exception handler **** * EXCEPT SUBQ.L #4,A7 Save space in stack for a PC value. LINK A6,#0 Frame pointer for accessing PC space. MOVEM.L A0-A5/D0-D7,-(SP) Save registers. : : decide here if your code handles exception, if so, branch... : MOVE.L BUFVBR,A0 Pass exception to debugger; Get saved VBR. MOVE.
Using the 166Bug Debugger 166Bug>RD PC =00010000 SR =2708=TR:OFF_S._7_.N... VBR =00000000 USP =0000DFFC MSP =0000EFFC ISP* =0000FFFC SFC =0=F0 DFC =0=F0 CACR =0=........ D0 =00000001 D1 =00000001 D2 =00000000 D3 =00000000 D4 =00000000 D5 =00000002 D6 =00000000 D7 =00000000 A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000 A4 =00000000 A5 =00000000 A6 =00000000 A7 =0000FFFC 00010000 203900F0 0000 MOVE.L ($F00000).
Floating Point Support Floating Point Support The floating point unit (FPU) of the MC68040 microprocessor chip is supported in 166Bug. For MVME166Bug, the commands MD, MM, RM, and RS have been extended to allow display and modification of floating point data in registers and in memory. Floating point instructions can be assembled/disassembled with the DI option of the MD and MM commands.
Using the 166Bug Debugger Single Precision Real This format would appear in memory as: 1-bit sign field (1 binary digit) 8-bit biased exponent field (2 hex digits. Bias = $7F) 23-bit fraction field 4 (6 hex digits) A single precision number takes 4 bytes in memory. Double Precision Real This format would appear in memory as: 1-bit sign field (1 binary digit) 11-bit biased exponent field (3 hex digits.
Floating Point Support Packed Decimal Real This format would appear in memory as: 4-bit sign field (4 binary digits) 16-bit exponent field (4 hex digits) 68-bit mantissa field (17 hex digits) 4 A packed decimal number takes 12 bytes in memory. Scientific Notation This format provides a convenient way to enter and display a floating point decimal number. Internally, the number is assembled into a packed decimal number and then converted into a number of the specified data type.
Using the 166Bug Debugger The 166Bug Debugger Command Set The 166Bug debugger commands are summarized in Table 4-3. The command syntax is shown using the symbols explained earlier in this chapter. The CNFG and ENV commands are explained in Appendix A. Controllers, devices, and their LUNs are listed in Appendix B or Appendix C. All other command details are explained in the MVME167Bug Debugging Package User’s Manual. Table 4-3.
The 166Bug Debugger Command Set Table 4-3.
Using the 166Bug Debugger Table 4-3.
CONFIGURE AND ENVIRONMENT COMMANDS A Configure Board Information Block CNFG [;[I][M]] This command is used to display and configure the board information block. This block is resident within the Non-Volatile RAM (NVRAM). Refer to the MVME166 Single Board Computer User’s Manual for the actual location. The information block contains various elements detailing specific operation parameters of the hardware.
A Configure and Environment Commands Using the I option initializes the unused area of the board information block to zero. Modification is permitted by using the M option of the command. At the end of the modification session, you are prompted for the update to Non-Volatile RAM (NVRAM). A Y response must be made for the update to occur; any other response terminates the update (disregards all changes). The update also recalculates the checksum. Be cautious when modifying parameters.
Set Environment to Bug/Operating System The parameters to be configured are listed in the following table: Table A-1. ENV Command Parameters ENV Parameter and Options Default Meaning of Default Bug or System environment [B/S] S System mode Field Service Menu Enable [Y/N] Y Display field service menu.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Auto Boot Default String [Y(NULL String)/(String)] Meaning of Default You may specify a string (filename) which is passed on to the code being booted. Maximum length is 16 characters. Default is the null string. ROM Boot Enable [Y/N] N ROMboot function is disabled. ROM Boot at power-up only [Y/N] Y ROMboot is attempted at power up only.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Network Autoboot Configuration Parameters Pointer (NVRAM) 00000000 This is the address where the network interface configuration parameters are to be saved/retained in NVRAM; these parameters are the necessary parameters to perform an unattended network boot.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Memory Search Delay Enable [Y/N] Memory Search Delay Address Memory Size Enable [Y/N] Default Meaning of Default N There will be no delay before the Bug begins its search for a work page. FFFFCE0F Default address is $FFFFCE0F.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Size of Local Memory Board #0 Size of Local Memory Board #1 Default 02000000 00000000 Meaning of Default You are prompted twice, once for each possible MVME166 memory board. Default is the calculated size of the memory board. Slave address decoders setup. The slave address decoders are use to allow another VMEbus master to access a local resource of the MVME166.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Slave Starting Address #2 FFE00000 Base address of the local resource that is accessible by the VMEbus. Default is the base address of static RAM, $FFE00000. Slave Ending Address #2 FFE1FFFF Ending address of the local resource that is accessible by the VMEbus. Default is the end of static RAM, $FFE1FFFF.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Master Ending Address #2 Default Meaning of Default 00000000 Ending address of the VMEbus resource that is accessible from the local bus. Default is $00000000. Master Control #2 00 Defines the access characteristics for the address space defined with this master address decoder. Default is $00. Master Enable #3 [Y/N] N Yes, setup and enable the Master Address Decoder #3.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Master Address Translation Address #4 00000000 This register will allow the VMEbus address and the local address to be different. The value in this register is the base address of VMEbus resource that is associated with the starting and ending address selections from the previous questions. Default is 0.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default VMEC2 GCSR Group Base Address CC Specifies the group address ($FFFFXX00) in Short I/O for this board. Default = $CC. VMEC2 GCSR Board Base Address 00 Specifies the base address ($FFFFCCXX) in Short I/O for this board. Default = $00. VMEbus Global Time Out Code 01 This controls the VMEbus timeout when systems controller. Default $01 = 64 µs.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default 00000000 Address offset for the first VSB to local bus map decoder. The upper 16 bits of this field will be added to the upper 16 bits of the VSB address received. This sum is then the address driven onto the local bus address lines. Default = 00000000. 0400 The bits in this register control various aspects of how the first VSB to local bus map decoder will operate.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default 01000000 The bits in this register control aspects of the local board’s access of the VSB.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default 0030 The bits in this register control various aspects of how the local bus to VSB map decoder #1 will operate. Consult the VSBchip2 register definition in the MVME166 programmer’s reference guide for a detailed explanation of each bit. Default = 0030.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default VSBC2 Master Ending Address #3 00000000 Ending address of an address range for the local bus to VSB map decoder #3. Only the upper 16 bits of this field are significant (or used). Default = 00000000. VSBC2 Master Address Offset #3 00000000 Address offset for the local bus to VSB map decoder #3.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options VSBC2 Master Attributes #4 A-16 Default Meaning of Default 0030 The bits in this register control various aspects of how the local bus to VSB map decoder #4 will operate. Consult the VSBchip2 register definition in the MVME166 programmer’s reference guide for a detailed explanation of each bit. Default = 0030.
DISK/TAPE CONTROLLER DATA B Disk/Tape Controller Modules Supported The following VMEbus disk/tape controller modules are supported by the 166Bug. The default address for each controller type is First Address and the controller can be addressed by First CLUN during commands BH, BO, or IOP, or during TRAP #15 calls .DSKRD or .DSKWR.
Disk/Tape Controller Data B Disk/Tape Controller Default Configurations NOTE: SCSI Common Command Set (CCS) devices are only the ones tested by Motorola Computer Group.
Disk/Tape Controller Default Configurations MVME323 -- 4 Devices Controller LUN Address 8 $FFFFA000 9 $FFFFA200 B Device LUN 0 1 2 3 Device Type ESDI Winchester hard drive ESDI Winchester hard drive ESDI Winchester hard drive ESDI Winchester hard drive MVME327A -- 9 Devices Controller LUN Address 2 $FFFFA600 3 $FFFFA700 MVME166IG/D2 Device LUN Device Type 00 10 20 30 40 50 60 SCSI Common Command Set (CCS), which may be any of these: 80 81 Local floppy drive - Fixed direct access - Remo
Disk/Tape Controller Data MVME328 -- 14 Devices B Controller LUN Address 6 $FFFF9000 7 $FFFF9800 16 $FFFF4800 17 $FFFF5800 18 $FFFF7000 19 $FFFF7800 Device LUN Device Type 00 08 10 18 20 28 30 SCSI Common Command Set (CCS), which may be any of these: - Removable flexible direct access (TEAC style) - CD-ROM - Sequential access 40 48 50 58 60 68 70 Same as above, but these will only be available if the daughter card for the second SCSI channel is present.
IOT Command Parameters for Supported Floppy Types IOT Command Parameters for Supported Floppy Types The following table lists the proper IOT command parameters for floppies used with boards such as the MVME328, MVME166, and MVME187.
Disk/Tape Controller Data B B-6 MVME166 Single Board Computer Installation Guide
NETWORK CONTROLLER DATA C Network Controller Modules Supported The following VMEbus network controller modules are supported by the MVME166Bug. The default address for each type and position is showed to indicate where the controller must reside to be supported by the MVME166Bug. The controllers are accessed via the specified CLUN and DLUNs listed here.
Network Controller Data C C-2 MVME166 Single Board Computer Installation Guide
Index When using this index, keep in mind that a page number indicates only where referenced material begins. It may extend to the page or pages following the page referenced.
Index CISC Single Board Computer(s) (SBC) B-1 Clear To Send (CTS) 3-6 CLUN (controller LUN) B-2, C-1 command identifier 4-1 command line 4-1 configuration, default disk/tape controller B-2 configuration, hardware 3-4 Configure (CNFG) and Environment (ENV) commands A-1 Configure Board Information Block (CNFG) A-1 connector J9 4-8 connectors 1-17 console port 4-8 control bit 1-7 controller B-1 controller LUN (CLUN) B-2, C-1 count 4-2 creating a new vector table 4-13 CTS (Clear To Send) 3-6 D I N D E X dat
Flash memory and download EPROM 1-10 flexible diskette B-2 floating point instructions 4-17 floating point support 4-17 floating point unit (FPU) 4-17, 4-19 floppy disk command parameters B-5 floppy diskette B-4 floppy drive B-2, B-3 four-byte 1-7 FPU (floating point unit) 4-17, 4-19 front panel switches and indicators 1-9 functional description 1-9 fuse F2 2-9 fuses F1, F3, and F4 2-9 G GCSR (Global Control and Status Registers) 2-9, 3-23 GCSR GPCSR0 A-6 GCSR method 3-23 general purpose readable jumpers o
Index M I N D E X mantissa field 4-17 manual terminology 1-6 MC68040 MPU 1-10 MC68040 TRAP instructions 4-9 MC68230 Parallel Interface/Timer (PIT) 1-14 memory maps 1-18 local bus 1-18 local I/O devices 1-20 VMEbus 1-22 VMEbus short I/O 1-22 VSB 1-22 memory requirements 3-13 metasymbols 4-2 MK48T08 (see Battery Backed Up RAM, BBRAM, and NVRAM) 1-13 MPAR (Multiprocessor Address Register) 3-22 MPCR (Multiprocessor Control Register) method 3-21 MPU clock speed calculation 3-13 Multiprocessor Address Register
PIT (MC68230 Parallel Interface/Timer) 1-14 port 0 or 00 4-8 port 1 or 01 4-8 port number(s) 4-1, 4-8 preserving the debugger operating environment 4-9 programmable tick timers 1-17 pseudo-registers 4-6 Q QIC-02 streaming tape drive B-4 R range 4-2 RARP/ARP protocol modules 3-20 related documentation 1-2 relative address+offset 4-6 requirements 1-5 reset 3-11 RESET switch 1-9 restarting the system 3-11 RFI 2-7 ROMboot 3-10 S SBC (see CISC Single Board Computer(s)) B-1 SCC (Sereial Controller Chip) (see C
Index TFTP protocol module 3-20 tick timers 1-16 timeout 1-17 transfer type (TT) 1-18 TRAP #15 4-9 true 1-7 TT (transfer type) 1-18 TTL 1-14 two-byte 1-7 U UDP/IP protocol modules 3-19 unpacking instructions 2-1 using 166Bug target vector table 4-12 using the 166Bug debugger 4-1 V V.
