User`s manual

Debug Trace Memory Structure 5-2
Example 5-4
User Level Setup 5-4
Code Level Setup 5-5
Debug Trace Display 5-6
Firmware Debug Log Map 5-9
Firmware Debug Log Entry Descriptions 5-11
BERR 5-11
BRST 5-11
COMP 5-11
DISC 5-12
IDOV 5-12
INIT 5-12
INT 5-12
KICK 5-12
LCMP 5-13
MREJ 5-13
PMM 5-13
PVER 5-13
QEKO 5-13
RESL 5-14
SGE 5-14
SIID 5-14
STEP 5-14
STO 5-14
UDC 5-14
XMSG 5-15
XSTO 5-15
Use of the Firmware After Use by the SBC ROM Debugger 5-15
Cache Coherency 5-16
Local Bus Usage by the NCR 53C710 5-16
Target Mode 5-17
Introduction B-1
siop_struc (Command Structure) B-1
User ID B-3
Command Control B-3
Bit 31 -- INTATR B-3
Bit 30 -- TARGET B-4
Bit 29 -- CONFIG B-4
Bit 18 -- PAR B-4
Bit 17 -- FIRST B-4