Personal Computer User Manual

Board Level Hardware Description
1-2 Installation Guide
1
The BusSwitch ASIC provides an interface between the processor bus
(MC88110 bus) and the local peripheral bus (MC68040 compatible bus). Refer
to the MVME197LE block diagram (Figure 1-1). It provides bus arbitration for
the MC88110 bus and serves as a seven level interrupt handler. It has
programmable map decoders for both busses, as well as write post buffers on
each, two tick timers, and four 32-bit general purpose registers.
The DCAM (DRAM Controller and Address Multiplexer) ASIC provides the
address multiplexers and RAS/CAS/WRITE control for the DRAM as well as
data control for the ECDM.
The ECDM (Error Correction and Data Multiplexer) ASIC multiplexes
between four data paths on the DRAM array. Since the device handles 16 bits,
four such devices are required on the MVME197LE to accommodate the 64-bit
data bus of the MC88110 microprocessor. Single-bit error correction and
double-bit detection is performed in the ECDM.
The PCCchip2 (Peripheral Channel Controller) ASIC provides two tick timers
and the interface to the LAN chip, the SCSI chip, the serial port chip, the
printer port, and the BBRAM (Battery Backup RAM).
A VMEbus interface chip with an MC68040 bus interface is one ASIC called the
VMEchip2. The VMEchip2 includes two tick timers, a watchdog timer,
programmable map decoders for the master and slave interfaces, and a
VMEbus to/from the local peripheral bus DMA controller, a VMEbus to/from
the local peripheral bus non-DMA programmed access interface, a VMEbus
interrupter, a VMEbus system controller, a VMEbus interrupt handler, and a
VMEbus requester.
Local peripheral bus to VMEbus transfers can be D8, D16, or D32. VMEchip2
DMA transfers to the VMEbus, however, can be 64 bits wide as Block Transfer
(BLT).
Requirements
These boards are designed to conform to the requirements of the following
documents:
❏ VMEbus Specification (IEEE 1014-87)
❏ EIA-232-D Serial Interface Specification, EIA
❏ SCSI Specification, ANSI