Personal Computer User Manual

Memory Maps
MVME197LEIG/D1 1-13
1
µsec, 64 µsec, 256 µsec, or infinite for the local peripheral bus. The local
peripheral bus timer does not operate during VMEbus bound cycles. VMEbus
bound cycles are timed by the VMEbus access timer and the VMEbus global
timer.
Interrupt Sources
MVME197LE MPU interrupts are channeled through the BusSwitch. They
may come from internal BusSwitch sources as well as from the PCCchip2 (IPL
inputs to the BusSwitch), the VMEchip2 (XIPL inputs to the BusSwitch), and
other external sources (PALINT and IRQ). The BusSwitch may also generate
the non-maskable interrupt (NMI) signal to the MPU from the ABORT push-
button switch. Refer to the BusSwitch, PCCchip2, and VMEchip2 chapters in the
MVME197LE, MVME197DP, and MVME197SP Single Board Computers
Programmer’s Reference Guide for more detailed information.
Connectors
The MVME197LE has two 64-position DIN connectors: P1 and P2. Connector
P1 rows A, B, C, and connector P2 row B provide the VMEbus interconnection.
Connector P2 rows A and C provide the interconnect to the SCSI bus, the serial
ports, the Ethernet interface, and the Centronics printer. There is a 249-pin
mezzanine connector (J2) with the MC88110 bus interface. This mezzanine
connector is for other MVME197 module expansion. On the MVME197LE
there is also a 20-pin general purpose connector (J1) which provides the
interconnect to the LEDs and the reset and abort signals. This connector is
different for the other modules in the MVME197 series. Refer to the board
specific SIMVME197 Single Board Computer Support Information manual for
detailed connector signal descriptions.
Memory Maps
There are three points of view for the memory maps: 1) the mapping of all
resources as viewed by the Processor Bus (MC88110 bus), 2) the mapping of
onboard/off-board resources as viewed from the Local Peripheral Bus
(MC68040 compatible bus), and 3) the mapping of onboard resources as
viewed by VMEbus Masters (VMEbus memory map).
Processor Bus Memory Map
Care should be taken, since all three maps are programmable. It is
recommended that direct mapping from the Processor Bus to the Local
Peripheral Bus be used.