Computer Hardware User Manual
Table Of Contents
- Contents
- List of Figures
- List of Tables
- About This Manual
- Programming Issues
- Introduction
- Programming Interfaces
- Functional Description
- Memory Maps
- Interrupt Handling
- Cache Coherency (MVME167P)
- Cache Coherency (MVME177P)
- Using Bus Timers
- Indivisible Cycles
- Supervisor Stack Pointer (MC68060)
- Sources of Local Bus Errors
- Error Conditions
- MPU Parity Error
- MPU Offboard Error
- MPU TEA - Cause Unidentified
- MPU Local Bus Time-out
- DMAC VMEbus Error
- DMAC Parity Error
- DMAC Offboard Error
- DMAC LTO Error
- DMAC TEA - Cause Unidentified
- SCC Retry Error
- SCC Parity Error
- SCC Offboard Error
- SCC LTO Error
- LAN Parity Error
- LAN Offboard Error
- LAN LTO Error
- SCSI Parity Error
- SCSI Offboard Error
- SCSI LTO Error
- VMEchip2
- Introduction
- Functional Blocks
- LCSR Programming Model
- Programming the VMEbus Slave Map Decoders
- VMEbus Slave Ending Address Register 1
- VMEbus Slave Starting Address Register 1
- VMEbus Slave Ending Address Register 2
- VMEbus Slave Starting Address Register 2
- VMEbus Slave Address Translation Address Offset Register 1
- VMEbus Slave Address Translation Select Register 1
- VMEbus Slave Address Translation Address Offset Register 2
- VMEbus Slave Address Translation Select Register 2
- VMEbus Slave Write Post and Snoop Control Register 2
- VMEbus Slave Address Modifier Select Register 2
- VMEbus Slave Write Post and Snoop Control Register 1
- VMEbus Slave Address Modifier Select Register 1
- Programming the Local-Bus-to-VMEbus Map Decoders
- Local Bus Slave (VMEbus Master) Ending Address Register 1
- Local Bus Slave (VMEbus Master) Starting Address Register 1
- Local Bus Slave (VMEbus Master) Ending Address Register 2
- Local Bus Slave (VMEbus Master) Starting Address Register 2
- Local Bus Slave (VMEbus Master) Ending Address Register 3
- Local Bus Slave (VMEbus Master) Starting Address Register 3
- Local Bus Slave (VMEbus Master) Ending Address Register 4
- Local Bus Slave (VMEbus Master) Starting Address Register 4
- Local Bus Slave (VMEbus Master) Address Translation Address Register 4
- Local Bus Slave (VMEbus Master) Address Translation Select Register 4
- Local Bus Slave (VMEbus Master) Attribute Register 4
- Local Bus Slave (VMEbus Master) Attribute Register 3
- Local Bus Slave (VMEbus Master) Attribute Register 2
- Local Bus Slave (VMEbus Master) Attribute Register 1
- VMEbus Slave GCSR Group Address Register
- VMEbus Slave GCSR Board Address Register
- Local-Bus-to-VMEbus Enable Control Register
- Local-Bus-to-VMEbus I/O Control Register
- ROM Control Register
- Programming the VMEchip2 DMA Controller
- DMAC Registers
- EPROM Decoder, SRAM and DMA Control Register
- Local-Bus-to-VMEbus Requester Control Register
- DMAC Control Register 1 (bits 07)
- DMAC Control Register 2 (bits 815)
- DMAC Control Register 2 (bits 07)
- DMAC Local Bus Address Counter
- DMAC VMEbus Address Counter
- DMAC Byte Counter
- Table Address Counter
- VMEbus Interrupter Control Register
- VMEbus Interrupter Vector Register
- MPU Status and DMA Interrupt Count Register
- DMAC Status Register
- Programming the Tick and Watchdog Timers
- VMEbus Arbiter Time-Out Control Register
- DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register
- VME Access, Local Bus, and Watchdog Time-out Control Register
- Prescaler Control Register
- Tick Timer 1 Compare Register
- Tick Timer 1 Counter
- Tick Timer 2 Compare Register
- Tick Timer 2 Counter
- Board Control Register
- Watchdog Timer Control Register
- Tick Timer 2 Control Register
- Tick Timer 1 Control Register
- Prescaler Counter
- Programming the Local Bus Interrupter
- Local Bus Interrupter Status Register (bits 2431)
- Local Bus Interrupter Status Register (bits 1623)
- Local Bus Interrupter Status Register (bits 815)
- Local Bus Interrupter Status Register (bits 07)
- Local Bus Interrupter Enable Register (bits 2431)
- Local Bus Interrupter Enable Register (bits 1623)
- Local Bus Interrupter Enable Register (bits 815)
- Local Bus Interrupter Enable Register (bits 07)
- Software Interrupt Set Register (bits 815)
- Interrupt Clear Register (bits 2431)
- Interrupt Clear Register (bits 1623)
- Interrupt Clear Register (bits 815)
- Interrupt Level Register 1 (bits 2431)
- Interrupt Level Register 1 (bits 1623)
- Interrupt Level Register 1 (bits 815)
- Interrupt Level Register 1 (bits 07)
- Interrupt Level Register 2 (bits 2431)
- Interrupt Level Register 2 (bits 1623)
- Interrupt Level Register 2 (bits 815)
- Interrupt Level Register 2 (bits 07)
- Interrupt Level Register 3 (bits 2431)
- Interrupt Level Register 3 (bits 1623)
- Interrupt Level Register 3 (bits 815)
- Interrupt Level Register 3 (bits 07)
- Interrupt Level Register 4 (bits 2431)
- Interrupt Level Register 4 (bits 1623)
- Interrupt Level Register 4 (bits 815)
- Interrupt Level Register 4 (bits 07)
- Vector Base Register
- I/O Control Register 1
- I/O Control Register 2
- I/O Control Register 3
- Miscellaneous Control Register
- Programming the VMEbus Slave Map Decoders
- GCSR Programming Model
- PCCchip2
- Introduction
- Functional Description
- Overall Memory Map
- Programming Model
- Chip ID Register
- Chip Revision Register
- General Control Register
- Vector Base Register
- Programming the Tick Timers
- Tick Timer 1 Compare Register
- Tick Timer 1 Counter
- Tick Timer 2 Compare Register
- Tick Timer 2 Counter
- Prescaler Count Register
- Prescaler Clock Adjust Register
- Tick Timer 2 Control Register
- Tick Timer 1 Control Register
- General Purpose Input Interrupt Control Register
- General Purpose Input/Output Pin Control Register
- Tick Timer 2 Interrupt Control Register
- Tick Timer 1 Interrupt Control Register
- SCC Error Status and Interrupt Control Registers
- LANC Error Status and Interrupt Control Registers
- Programming the SCSI Error Status and Interrupt Registers
- Programming the Printer Port
- Printer ACK Interrupt Control Register
- Printer FAULT Interrupt Control Register
- Printer SEL Interrupt Control Register
- Printer PE Interrupt Control Register
- Printer BUSY Interrupt Control Register
- Printer Input Status Register
- Printer Port Control Register
- Chip Speed Register
- Printer Data Register
- Interrupt Priority Level Register
- Interrupt Mask Level Register
- MCECC Functions
- Introduction
- Features
- Functional Description
- General Description
- Performance
- Cache Coherency
- ECC
- Cycle Types
- Error Reporting
- Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Cycle Type = Burst Write
- Single Bit Error (Cycle Type = Non-Burst Write)
- Double Bit Error (Cycle Type = Non-Burst Write)
- Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write)
- Single Bit Error (Cycle Type = Scrub)
- Double Bit Error (Cycle Type = Scrub)
- Triple (or Greater) Bit Error (Cycle Type = Scrub)
- Error Logging
- Scrub
- Refresh
- Arbitration
- Chip Defaults
- Programming Model
- Chip ID Register
- Chip Revision Register
- Memory Configuration Register
- Base Address Register
- DRAM Control Register
- BCLK Frequency Register
- Data Control Register
- Scrub Control Register
- Scrub Period Register Bits 15-8
- Scrub Period Register Bits 7-0
- Chip Prescaler Counter
- Scrub Time On/Time Off Register
- Scrub Prescaler Counter (Bits 21-16)
- Scrub Prescaler Counter (Bits 15-8)
- Scrub Prescaler Counter (Bits 7-0)
- Scrub Timer Counter (Bits 15-8)
- Scrub Timer Counter (Bits 7-0)
- Scrub Address Counter (Bits 26-24)
- Scrub Address Counter (Bits 23-16)
- Scrub Address Counter (Bits 15-8)
- Scrub Address Counter (Bits 7-4)
- Error Logger Register
- Error Address (Bits 31-24)
- Error Address (Bits 23-16)
- Error Address (Bits 15-8)
- Error Address (Bits 7-4)
- Error Syndrome Register
- Defaults Register 1
- Defaults Register 2
- SDRAM Configuration Register
- Initialization
- Syndrome Decoding
- Summary of Changes
- Printer and Serial Port Connections
- Related Documentation
- Index
Functional Description
http://www.motorola.com/computer/literature 3-3
3
BBRAM Interface
The PCCchip2 provides a read/write interface to the BBRAM by any bus
master on the MC68040 bus. The PCCchip2 performs dynamic sizing for
accesses to the 8-bit BBRAM to make it appear contiguous. This feature
allows code to be executable from the BBRAM. The BBRAM device
access time must be no greater than 5 BCLK periods in fast mode or 9
BCLK periods in slow mode. The BBRAM speed option is controlled by
a control bit in the General Control Register.
82596CA LAN Controller Interface
The LAN controller interface is described in the following sections.
MPU Port and MPU Channel Attention
The PCCchip2 allows the (MC68040-compatible) Local Bus master to
communicate directly with the Intel 82596CA LAN Coprocessor by
providing a map decoder and required control and timing logic. Two types
of direct access are feasible with the 82596CA: MPU Port and MPU
Attention.
MPU Port access enables the MPU to write to an internal, 32-bit 82596CA
command register. This allows the MPU to do four things:
1. Write an alternate System Configuration Pointer address.
2. Write an alternative dump area pointer and perform a dump.
3. Execute a software reset.
4. Execute a self-test.
Each Port access must consist of two 16-bit writes: Upper Command Word
(two bytes) and Lower Command Word (two bytes). The Upper Command
Word (two bytes) is mapped at $FFF46000 and the Lower Command
Word (two bytes) is mapped at $FFF46002.
The PCCchip2 only supports (decodes) MPU Port writes. It does not
decode MPU Port reads. (Nor does the 82596CA support MPU Port reads.)