Computer Hardware User Manual
Table Of Contents
- Contents
- List of Figures
- List of Tables
- About This Manual
- Programming Issues
- Introduction
- Programming Interfaces
- Functional Description
- Memory Maps
- Interrupt Handling
- Cache Coherency (MVME167P)
- Cache Coherency (MVME177P)
- Using Bus Timers
- Indivisible Cycles
- Supervisor Stack Pointer (MC68060)
- Sources of Local Bus Errors
- Error Conditions
- MPU Parity Error
- MPU Offboard Error
- MPU TEA - Cause Unidentified
- MPU Local Bus Time-out
- DMAC VMEbus Error
- DMAC Parity Error
- DMAC Offboard Error
- DMAC LTO Error
- DMAC TEA - Cause Unidentified
- SCC Retry Error
- SCC Parity Error
- SCC Offboard Error
- SCC LTO Error
- LAN Parity Error
- LAN Offboard Error
- LAN LTO Error
- SCSI Parity Error
- SCSI Offboard Error
- SCSI LTO Error
- VMEchip2
- Introduction
- Functional Blocks
- LCSR Programming Model
- Programming the VMEbus Slave Map Decoders
- VMEbus Slave Ending Address Register 1
- VMEbus Slave Starting Address Register 1
- VMEbus Slave Ending Address Register 2
- VMEbus Slave Starting Address Register 2
- VMEbus Slave Address Translation Address Offset Register 1
- VMEbus Slave Address Translation Select Register 1
- VMEbus Slave Address Translation Address Offset Register 2
- VMEbus Slave Address Translation Select Register 2
- VMEbus Slave Write Post and Snoop Control Register 2
- VMEbus Slave Address Modifier Select Register 2
- VMEbus Slave Write Post and Snoop Control Register 1
- VMEbus Slave Address Modifier Select Register 1
- Programming the Local-Bus-to-VMEbus Map Decoders
- Local Bus Slave (VMEbus Master) Ending Address Register 1
- Local Bus Slave (VMEbus Master) Starting Address Register 1
- Local Bus Slave (VMEbus Master) Ending Address Register 2
- Local Bus Slave (VMEbus Master) Starting Address Register 2
- Local Bus Slave (VMEbus Master) Ending Address Register 3
- Local Bus Slave (VMEbus Master) Starting Address Register 3
- Local Bus Slave (VMEbus Master) Ending Address Register 4
- Local Bus Slave (VMEbus Master) Starting Address Register 4
- Local Bus Slave (VMEbus Master) Address Translation Address Register 4
- Local Bus Slave (VMEbus Master) Address Translation Select Register 4
- Local Bus Slave (VMEbus Master) Attribute Register 4
- Local Bus Slave (VMEbus Master) Attribute Register 3
- Local Bus Slave (VMEbus Master) Attribute Register 2
- Local Bus Slave (VMEbus Master) Attribute Register 1
- VMEbus Slave GCSR Group Address Register
- VMEbus Slave GCSR Board Address Register
- Local-Bus-to-VMEbus Enable Control Register
- Local-Bus-to-VMEbus I/O Control Register
- ROM Control Register
- Programming the VMEchip2 DMA Controller
- DMAC Registers
- EPROM Decoder, SRAM and DMA Control Register
- Local-Bus-to-VMEbus Requester Control Register
- DMAC Control Register 1 (bits 07)
- DMAC Control Register 2 (bits 815)
- DMAC Control Register 2 (bits 07)
- DMAC Local Bus Address Counter
- DMAC VMEbus Address Counter
- DMAC Byte Counter
- Table Address Counter
- VMEbus Interrupter Control Register
- VMEbus Interrupter Vector Register
- MPU Status and DMA Interrupt Count Register
- DMAC Status Register
- Programming the Tick and Watchdog Timers
- VMEbus Arbiter Time-Out Control Register
- DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register
- VME Access, Local Bus, and Watchdog Time-out Control Register
- Prescaler Control Register
- Tick Timer 1 Compare Register
- Tick Timer 1 Counter
- Tick Timer 2 Compare Register
- Tick Timer 2 Counter
- Board Control Register
- Watchdog Timer Control Register
- Tick Timer 2 Control Register
- Tick Timer 1 Control Register
- Prescaler Counter
- Programming the Local Bus Interrupter
- Local Bus Interrupter Status Register (bits 2431)
- Local Bus Interrupter Status Register (bits 1623)
- Local Bus Interrupter Status Register (bits 815)
- Local Bus Interrupter Status Register (bits 07)
- Local Bus Interrupter Enable Register (bits 2431)
- Local Bus Interrupter Enable Register (bits 1623)
- Local Bus Interrupter Enable Register (bits 815)
- Local Bus Interrupter Enable Register (bits 07)
- Software Interrupt Set Register (bits 815)
- Interrupt Clear Register (bits 2431)
- Interrupt Clear Register (bits 1623)
- Interrupt Clear Register (bits 815)
- Interrupt Level Register 1 (bits 2431)
- Interrupt Level Register 1 (bits 1623)
- Interrupt Level Register 1 (bits 815)
- Interrupt Level Register 1 (bits 07)
- Interrupt Level Register 2 (bits 2431)
- Interrupt Level Register 2 (bits 1623)
- Interrupt Level Register 2 (bits 815)
- Interrupt Level Register 2 (bits 07)
- Interrupt Level Register 3 (bits 2431)
- Interrupt Level Register 3 (bits 1623)
- Interrupt Level Register 3 (bits 815)
- Interrupt Level Register 3 (bits 07)
- Interrupt Level Register 4 (bits 2431)
- Interrupt Level Register 4 (bits 1623)
- Interrupt Level Register 4 (bits 815)
- Interrupt Level Register 4 (bits 07)
- Vector Base Register
- I/O Control Register 1
- I/O Control Register 2
- I/O Control Register 3
- Miscellaneous Control Register
- Programming the VMEbus Slave Map Decoders
- GCSR Programming Model
- PCCchip2
- Introduction
- Functional Description
- Overall Memory Map
- Programming Model
- Chip ID Register
- Chip Revision Register
- General Control Register
- Vector Base Register
- Programming the Tick Timers
- Tick Timer 1 Compare Register
- Tick Timer 1 Counter
- Tick Timer 2 Compare Register
- Tick Timer 2 Counter
- Prescaler Count Register
- Prescaler Clock Adjust Register
- Tick Timer 2 Control Register
- Tick Timer 1 Control Register
- General Purpose Input Interrupt Control Register
- General Purpose Input/Output Pin Control Register
- Tick Timer 2 Interrupt Control Register
- Tick Timer 1 Interrupt Control Register
- SCC Error Status and Interrupt Control Registers
- LANC Error Status and Interrupt Control Registers
- Programming the SCSI Error Status and Interrupt Registers
- Programming the Printer Port
- Printer ACK Interrupt Control Register
- Printer FAULT Interrupt Control Register
- Printer SEL Interrupt Control Register
- Printer PE Interrupt Control Register
- Printer BUSY Interrupt Control Register
- Printer Input Status Register
- Printer Port Control Register
- Chip Speed Register
- Printer Data Register
- Interrupt Priority Level Register
- Interrupt Mask Level Register
- MCECC Functions
- Introduction
- Features
- Functional Description
- General Description
- Performance
- Cache Coherency
- ECC
- Cycle Types
- Error Reporting
- Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Cycle Type = Burst Write
- Single Bit Error (Cycle Type = Non-Burst Write)
- Double Bit Error (Cycle Type = Non-Burst Write)
- Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write)
- Single Bit Error (Cycle Type = Scrub)
- Double Bit Error (Cycle Type = Scrub)
- Triple (or Greater) Bit Error (Cycle Type = Scrub)
- Error Logging
- Scrub
- Refresh
- Arbitration
- Chip Defaults
- Programming Model
- Chip ID Register
- Chip Revision Register
- Memory Configuration Register
- Base Address Register
- DRAM Control Register
- BCLK Frequency Register
- Data Control Register
- Scrub Control Register
- Scrub Period Register Bits 15-8
- Scrub Period Register Bits 7-0
- Chip Prescaler Counter
- Scrub Time On/Time Off Register
- Scrub Prescaler Counter (Bits 21-16)
- Scrub Prescaler Counter (Bits 15-8)
- Scrub Prescaler Counter (Bits 7-0)
- Scrub Timer Counter (Bits 15-8)
- Scrub Timer Counter (Bits 7-0)
- Scrub Address Counter (Bits 26-24)
- Scrub Address Counter (Bits 23-16)
- Scrub Address Counter (Bits 15-8)
- Scrub Address Counter (Bits 7-4)
- Error Logger Register
- Error Address (Bits 31-24)
- Error Address (Bits 23-16)
- Error Address (Bits 15-8)
- Error Address (Bits 7-4)
- Error Syndrome Register
- Defaults Register 1
- Defaults Register 2
- SDRAM Configuration Register
- Initialization
- Syndrome Decoding
- Summary of Changes
- Printer and Serial Port Connections
- Related Documentation
- Index
1-2 Computer Group Literature Center Web Site
Programming Issues
1
The Petra ASIC is functionally compatible with each of the components
that it replaces. In cases where functionality between ASICs is exclusive,
configuration switches or jumpers are provided to let you select the
desired functionality.
In several areas of functionality, the configuration switches provide
backward compatibility with earlier MVME167/177 implementations, but
you can override their settings in software if you wish. A “R/W” by the
corresponding register table entry in this manual denotes instances where
this override capability is present.
Where the older technology supported “fast page” or “EDO” DRAM
chips, the Petra memory controllers support SDRAM devices. The two
memory controllers modeled in Petra duplicate the functionality of the
“parity” memory controller found in the MC ASICs used on certain other
boards as well as that of the “single-bit error correcting/double-bit error
detecting” memory controller found in the MCECC ASICs used on the
MVME167/177.
This Programmer’s Reference Guide describes the MCECC model (in
Chapter 4). In the MVME167/177 application, there is logic on the Petra
chip to prevent you from inadvertently enabling the MC memory controller
model.
The same SDRAM memory array serves both controller models. The
SDRAM array is 32 data bits wide with 7 checkbits. The array architecture
is a non-interleaved single bank for sizes below 32MB. For array sizes
above 32MB, additional physical memory banks are added but the
architecture remains non-interleaved.
A final note on the SDRAM implementation: The bandwidth between the
SDRAM and local bus is greater than it was with the earlier DRAM array.
As a result, software takes less time to execute. Applications that
incorporate elapsed-time functions which are dependent on code
execution may have problems.
For readers who need to know the ASIC-specific differences between the
previous MCECC and Petra/MCECC programming models in detail,
certain areas of the text in this manual are printed in italics and marked
with change bars (as is done here). Readers should compare those sections
to the corresponding sections of the first- and second-generation manuals.