Computer Hardware User Manual
Table Of Contents
- Contents
- List of Figures
- List of Tables
- About This Manual
- Programming Issues
- Introduction
- Programming Interfaces
- Functional Description
- Memory Maps
- Interrupt Handling
- Cache Coherency (MVME167P)
- Cache Coherency (MVME177P)
- Using Bus Timers
- Indivisible Cycles
- Supervisor Stack Pointer (MC68060)
- Sources of Local Bus Errors
- Error Conditions
- MPU Parity Error
- MPU Offboard Error
- MPU TEA - Cause Unidentified
- MPU Local Bus Time-out
- DMAC VMEbus Error
- DMAC Parity Error
- DMAC Offboard Error
- DMAC LTO Error
- DMAC TEA - Cause Unidentified
- SCC Retry Error
- SCC Parity Error
- SCC Offboard Error
- SCC LTO Error
- LAN Parity Error
- LAN Offboard Error
- LAN LTO Error
- SCSI Parity Error
- SCSI Offboard Error
- SCSI LTO Error
- VMEchip2
- Introduction
- Functional Blocks
- LCSR Programming Model
- Programming the VMEbus Slave Map Decoders
- VMEbus Slave Ending Address Register 1
- VMEbus Slave Starting Address Register 1
- VMEbus Slave Ending Address Register 2
- VMEbus Slave Starting Address Register 2
- VMEbus Slave Address Translation Address Offset Register 1
- VMEbus Slave Address Translation Select Register 1
- VMEbus Slave Address Translation Address Offset Register 2
- VMEbus Slave Address Translation Select Register 2
- VMEbus Slave Write Post and Snoop Control Register 2
- VMEbus Slave Address Modifier Select Register 2
- VMEbus Slave Write Post and Snoop Control Register 1
- VMEbus Slave Address Modifier Select Register 1
- Programming the Local-Bus-to-VMEbus Map Decoders
- Local Bus Slave (VMEbus Master) Ending Address Register 1
- Local Bus Slave (VMEbus Master) Starting Address Register 1
- Local Bus Slave (VMEbus Master) Ending Address Register 2
- Local Bus Slave (VMEbus Master) Starting Address Register 2
- Local Bus Slave (VMEbus Master) Ending Address Register 3
- Local Bus Slave (VMEbus Master) Starting Address Register 3
- Local Bus Slave (VMEbus Master) Ending Address Register 4
- Local Bus Slave (VMEbus Master) Starting Address Register 4
- Local Bus Slave (VMEbus Master) Address Translation Address Register 4
- Local Bus Slave (VMEbus Master) Address Translation Select Register 4
- Local Bus Slave (VMEbus Master) Attribute Register 4
- Local Bus Slave (VMEbus Master) Attribute Register 3
- Local Bus Slave (VMEbus Master) Attribute Register 2
- Local Bus Slave (VMEbus Master) Attribute Register 1
- VMEbus Slave GCSR Group Address Register
- VMEbus Slave GCSR Board Address Register
- Local-Bus-to-VMEbus Enable Control Register
- Local-Bus-to-VMEbus I/O Control Register
- ROM Control Register
- Programming the VMEchip2 DMA Controller
- DMAC Registers
- EPROM Decoder, SRAM and DMA Control Register
- Local-Bus-to-VMEbus Requester Control Register
- DMAC Control Register 1 (bits 07)
- DMAC Control Register 2 (bits 815)
- DMAC Control Register 2 (bits 07)
- DMAC Local Bus Address Counter
- DMAC VMEbus Address Counter
- DMAC Byte Counter
- Table Address Counter
- VMEbus Interrupter Control Register
- VMEbus Interrupter Vector Register
- MPU Status and DMA Interrupt Count Register
- DMAC Status Register
- Programming the Tick and Watchdog Timers
- VMEbus Arbiter Time-Out Control Register
- DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register
- VME Access, Local Bus, and Watchdog Time-out Control Register
- Prescaler Control Register
- Tick Timer 1 Compare Register
- Tick Timer 1 Counter
- Tick Timer 2 Compare Register
- Tick Timer 2 Counter
- Board Control Register
- Watchdog Timer Control Register
- Tick Timer 2 Control Register
- Tick Timer 1 Control Register
- Prescaler Counter
- Programming the Local Bus Interrupter
- Local Bus Interrupter Status Register (bits 2431)
- Local Bus Interrupter Status Register (bits 1623)
- Local Bus Interrupter Status Register (bits 815)
- Local Bus Interrupter Status Register (bits 07)
- Local Bus Interrupter Enable Register (bits 2431)
- Local Bus Interrupter Enable Register (bits 1623)
- Local Bus Interrupter Enable Register (bits 815)
- Local Bus Interrupter Enable Register (bits 07)
- Software Interrupt Set Register (bits 815)
- Interrupt Clear Register (bits 2431)
- Interrupt Clear Register (bits 1623)
- Interrupt Clear Register (bits 815)
- Interrupt Level Register 1 (bits 2431)
- Interrupt Level Register 1 (bits 1623)
- Interrupt Level Register 1 (bits 815)
- Interrupt Level Register 1 (bits 07)
- Interrupt Level Register 2 (bits 2431)
- Interrupt Level Register 2 (bits 1623)
- Interrupt Level Register 2 (bits 815)
- Interrupt Level Register 2 (bits 07)
- Interrupt Level Register 3 (bits 2431)
- Interrupt Level Register 3 (bits 1623)
- Interrupt Level Register 3 (bits 815)
- Interrupt Level Register 3 (bits 07)
- Interrupt Level Register 4 (bits 2431)
- Interrupt Level Register 4 (bits 1623)
- Interrupt Level Register 4 (bits 815)
- Interrupt Level Register 4 (bits 07)
- Vector Base Register
- I/O Control Register 1
- I/O Control Register 2
- I/O Control Register 3
- Miscellaneous Control Register
- Programming the VMEbus Slave Map Decoders
- GCSR Programming Model
- PCCchip2
- Introduction
- Functional Description
- Overall Memory Map
- Programming Model
- Chip ID Register
- Chip Revision Register
- General Control Register
- Vector Base Register
- Programming the Tick Timers
- Tick Timer 1 Compare Register
- Tick Timer 1 Counter
- Tick Timer 2 Compare Register
- Tick Timer 2 Counter
- Prescaler Count Register
- Prescaler Clock Adjust Register
- Tick Timer 2 Control Register
- Tick Timer 1 Control Register
- General Purpose Input Interrupt Control Register
- General Purpose Input/Output Pin Control Register
- Tick Timer 2 Interrupt Control Register
- Tick Timer 1 Interrupt Control Register
- SCC Error Status and Interrupt Control Registers
- LANC Error Status and Interrupt Control Registers
- Programming the SCSI Error Status and Interrupt Registers
- Programming the Printer Port
- Printer ACK Interrupt Control Register
- Printer FAULT Interrupt Control Register
- Printer SEL Interrupt Control Register
- Printer PE Interrupt Control Register
- Printer BUSY Interrupt Control Register
- Printer Input Status Register
- Printer Port Control Register
- Chip Speed Register
- Printer Data Register
- Interrupt Priority Level Register
- Interrupt Mask Level Register
- MCECC Functions
- Introduction
- Features
- Functional Description
- General Description
- Performance
- Cache Coherency
- ECC
- Cycle Types
- Error Reporting
- Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)
- Cycle Type = Burst Write
- Single Bit Error (Cycle Type = Non-Burst Write)
- Double Bit Error (Cycle Type = Non-Burst Write)
- Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write)
- Single Bit Error (Cycle Type = Scrub)
- Double Bit Error (Cycle Type = Scrub)
- Triple (or Greater) Bit Error (Cycle Type = Scrub)
- Error Logging
- Scrub
- Refresh
- Arbitration
- Chip Defaults
- Programming Model
- Chip ID Register
- Chip Revision Register
- Memory Configuration Register
- Base Address Register
- DRAM Control Register
- BCLK Frequency Register
- Data Control Register
- Scrub Control Register
- Scrub Period Register Bits 15-8
- Scrub Period Register Bits 7-0
- Chip Prescaler Counter
- Scrub Time On/Time Off Register
- Scrub Prescaler Counter (Bits 21-16)
- Scrub Prescaler Counter (Bits 15-8)
- Scrub Prescaler Counter (Bits 7-0)
- Scrub Timer Counter (Bits 15-8)
- Scrub Timer Counter (Bits 7-0)
- Scrub Address Counter (Bits 26-24)
- Scrub Address Counter (Bits 23-16)
- Scrub Address Counter (Bits 15-8)
- Scrub Address Counter (Bits 7-4)
- Error Logger Register
- Error Address (Bits 31-24)
- Error Address (Bits 23-16)
- Error Address (Bits 15-8)
- Error Address (Bits 7-4)
- Error Syndrome Register
- Defaults Register 1
- Defaults Register 2
- SDRAM Configuration Register
- Initialization
- Syndrome Decoding
- Summary of Changes
- Printer and Serial Port Connections
- Related Documentation
- Index
http://www.motorola.com/computer/literature IN-7
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local bus interrupter registers
I/O Control register 1 2-96
I/O Control register 2 2-97
I/O Control register 3 2-97
Interrupt Level register 4 (bits 0-7) 2-95
Miscellaneous Control register 2-98
Status register (bits 16-23) 2-78
Status register (bits 24-31) 2-77
Vector Base register 2-95
local bus master 2-9
VMEbus and 2-10
local bus slave (VMEbus master) registers
Address Translation Address Register 4
2-42
Address Translation Select Register 4
2-42
Attribute Register 1 2-46
Attribute Register 2 2-45
Attribute Register 3 2-44
Attribute Register 4 2-43
Ending Address Register 1 2-39
Ending Address Register 2 2-40
Ending Address Register 3 2-41
Ending Address Register 4 2-41
Starting Address Register 1 2-40
Starting Address Register 2 2-40
Starting Address Register 3 2-41
Starting Address Register 4 2-42
local bus slave, composition of 2-4
local bus timer
VMEchip2 ASIC 2-18
local control and status segisters (LCSRs),
VMEbus 2-7
local I/O devices memory map 1-22
local reset driver, VMEbus 2-18
local reset, VMEbus 2-18
local SCSI ID 1-45
local-bus-to-VMEbus
Enable Control register 2-49
I/O Control register 2-50
interface 1-18
interface, VMEchip2 2-4
map decoders, programming 2-37
requester 2-7
requester register, programming 2-51
location monitor
interrupters, VMEbus 2-19
status register (VMEchip2 ASIC) 2-101
location monitors LM0-LM3 (VMEchip2
ASIC) 2-100
LVFAIR bit (VMEchip2 ASIC) 2-8
M
M48T58 BBRAM, TOD Clock memory map
1-42
manual strobe control 3-45
map decoders 2-37
GCSR 1-46
SDRAM 1-11
VMEbus interface 1-46
VMEchip2 ASIC 2-4, 2-6, 2-9
master interrupt enable (MIEN) bit 2-74,
2-96
master interrupt enable (PCCchip2 ASIC)
3-15
MC68040
bus master support for 82596C 3-4
MPU 1-7
MC68060
MPU 1-7
MC680x0
indivisible RMW memory accesses 1-52
MOVE16 access 3-10
normal access 3-10
MCECC chip Memory Controller ASIC 1-3
MCECC internal register memory map 1-34
MCECC sector
arbitration process 4-9
Base Address register 4-15
BCLK Frequency register 4-16
chip defaults 4-9
Chip Prescaler counter 4-21
Data Control register 4-17
Defaults register 1 4-30