Technical data

4-4 Computer Group Literature Center Web Site
Functional Description
4
Block Diagram
The block diagram in Figure 4-1 on page 4-5 illustrates the MVME177P’s
overall architecture.
Functional Description
This section contains a functional description of the major blocks on the
MVME177P.
Data Bus Structure
The local data bus on the MVME177P is a 32-bit synchronous bus that is
based on the MC68060 bus, and which supports burst transfers and
snooping. The various local bus master and slave devices use the local bus
to communicate. The local bus is arbitrated by priority type; the priority of
the local bus masters from highest to lowest is: 82596CA LAN, CD2401
serial (through the PCCchip2), 53C710 SCSI, VMEbus, and MPU. In the
general case, any master can access any slave; not all combinations pass
the common sense test, however. Refer to the MVME1X7P Single Board
Computers Programmer’s Reference Guide and to the user's guide for each
device to determine its port size, data bus connection, and any restrictions
that apply when accessing the device.
Microprocessor
The MC68060 processor is used on the MVME177P. The MC68060 has
on-chip instruction and data caches and a floating-point processor. Refer
to the MC68060 user's manual for more information.