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MVME5100

Single Board Computer

Programmer’s

Reference Guide

V5100A/PG3

July 2003 Edition

Summary of content (330 pages)

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MVME5100 Single Board Computer Programmer’s Reference Guide V5100A/PG3 July 2003 Edition
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© Copyright 2003 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola and the Motorola logo are registered trademarks and AltiVec is a trademark of Motorola, Inc. PowerPC and the PowerPC logo are registered trademarks; and PowerPC 750 is a trademark of International Business Machines Corporation and are used by Motorola, Inc. under license from International Business Machines Corporation.
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Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware.
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Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution ! Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection. Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry.
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CE Notice (European Community) Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC).
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Limited and Restricted Rights Legend If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.
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Contents About This Manual Summary of Changes ...............................................................................................xviii Overview of Contents ..............................................................................................xviii Comments and Suggestions .......................................................................................xix Conventions Used in This Manual.............................................................................xix Terminology.....
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The Universe ASIC .......................................................................................... 1-17 PCI Configuration Space.................................................................................. 1-19 Hawk External Register Bus Address Assignments......................................... 1-21 MVME5100 Hawk External Register Bus Summary ............................... 1-21 Dual TL16C550 UARTs...................................................................................
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PCI Slave ...................................................................................................2-22 PCI FIFO ...................................................................................................2-26 PCI Master .................................................................................................2-26 Generating PCI Cycles ..............................................................................2-29 PCI Arbiter .......................................................
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Interrupt Acknowledge Register ............................................................... 2-65 8259 Mode ................................................................................................ 2-65 Current Task Priority Level ...................................................................... 2-65 Architectural Notes........................................................................................... 2-66 Effects of Interrupt Serialization .............................................
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Spurious Vector Register.........................................................................2-118 Timer Frequency Register .......................................................................2-118 Timer Current Count Registers................................................................2-119 Timer Basecount Registers......................................................................2-120 Timer Vector/Priority Registers ..............................................................
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Error Logging............................................................................................ 3-13 ROM/Flash Interface ........................................................................................ 3-14 ROM/Flash Speeds.................................................................................... 3-19 I2C Interface..................................................................................................... 3-22 I2C Byte Write ..............................................
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Address Parity Error Log Register ............................................................3-71 Address Parity Error Address Register......................................................3-72 32-Bit Counter ...........................................................................................3-73 External Register Set .................................................................................3-73 tben Register ....................................................................................
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APPENDIX B MVME5100 VPD Reference Information Vital Product Data (VPD) Introduction .................................................................... B-1 How to Read the VPD Information ................................................................... B-1 How to Modify the VPD Information ............................................................... B-2 What Happens if the VPD Information is Corrupted? ...................................... B-3 How to Fix Corrupted VPD Information .................
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List of Figures Figure 1-1. MVME5100 Block Diagram ...................................................................1-3 Figure 1-2. VMEbus Master Mapping.....................................................................1-18 Figure 2-1. Hawk PCI Host Bridge Block Diagram ..................................................2-3 Figure 2-2. PPC to PCI Address Decoding................................................................2-6 Figure 2-3. PPC to PCI Address Translation ................................
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List of Tables Table 1-1. MVME Key Features ................................................................................1-1 Table 1-2. Default Processor Memory Map...............................................................1-4 Table 1-3. Suggested CHRP Memory Map ...............................................................1-6 Table 1-4. Hawk PPC Register Values for Suggested Memory Map.........................1-7 Table 1-5. I2C Device Addressing ....................................................
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Table 2-13. Address Modification for Little Endian Transfers ............................... 2-40 Table 2-14. WDTxCNTL Programming ................................................................. 2-44 Table 2-15. PHB Hardware Configuration .............................................................. 2-50 Table 2-16. PPC Register Map for PHB.................................................................. 2-68 Table 2-17. PCI Configuration Register ........................................................
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Table 4-1. MPIC Interrupt Assignments ....................................................................4-1 Table 4-2. PBC ISA Interrupt Assignments...............................................................4-3 Table 4-3. Error Notification and Handling ...............................................................4-6 Table A-1. Motorola Computer Group Documents .................................................A-1 Table A-2. Manufacturers’ Documents ...................................................
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About This Manual The MVME5100 Single Board Computer Programmer’s Guide provides the information you will need to program and configure your MVME5100 Single Board Computer. It provides specific programming information and data applicable to this board. This guide provides programming information and other data applicable to the MVME5100. As an added convienience, it also provides details of the chip set (Hawk) programming functions.
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As of the printing date of this manual, the MVME5100 is available in the configurations shown below.
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Part Number Description MVME761-011 Transition module: Two DB-9 async serial port connectors, two HD-26 sync/async serial port connectors, one HD-36 parallel port connector, and one RJ-45 10/100 Ethernet connector; includes 5-row DIN P2 adapter module and cable (for 16-bit SCSI); requires backplane with 5-row DIN connectors. SIM232DCE or DTE EIA-232 DCE or DTE Serial Interface Module SIM530DCE or DTE EIA-530 DCE or DTE Serial Interface Module SIMV35DCE or DTE V.
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Summary of Changes The following changes were made for the 2nd revision of this manual. Date Doc. Rev Changes 09/2001 V5100A/PG2 Memory Maps and additional register information was added to Chapter 1. Corrections were made to Table 4-1 in Chapter 4. Additions were made to Appendix A, Releated Documentation. Appendix B, VPD Information was added. This section titled "About this Manual" was also added. 07/2003 v5100A/PG3 Added information at the end of Chapter 1 on IPMC7xx ISA Bus Resources.
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8259 Interrupts, and a description of certain exceptions such as sources of reset, error notification and handling, endian issues, and processor/Hawk relationships. Appendix A, Related Documentation, provides a listing of related Motorola manuals, vendor documentation and industry specifications. Appendix B, MVME5100 VPD Reference Information, provides an explanation of the VPD reference information including certain "How to" info, as well as specific VPD Data Definitions.
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is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms. courier is used for system output (for example, screen displays, reports), examples, and system prompts. , or represents the carriage return or Enter key.
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In this manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent. Data and address sizes are defined as follows: Byte 8 bits, numbered 0 through 7, with bit 0 being the least significant.
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1Product Data and Memory Maps 1 Introduction The MVME5100 is a state-of-the-art Single Board Computer. It incorporates Motorola’s PowerPlus II architecture with a choice of PowerPC processors—either Motorola’s MPC7410 with AltiVec™ technology for algorithmic intensive computations or the low-power MPC750 or MPC755. The MVME5100 incorporates a highly optimized PCI interface and memory controller enabling up to 582MB/s memory read bandwidth and 640MB/s burst write bandwidth.
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1 Product Data and Memory Maps Table 1-1.
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Introduction 100 MHz MPC604 Processor Bus The following block diagram illustrates the architecture of the MVME5100 Single Board Computer.
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1 Product Data and Memory Maps Memory maps The following sections describe the memory maps for the MVME5100. Processor Memory Map The processor memory map configuration is under the control of the PCI Host Bridge (PHB) and System Memory Controller (SMC) portions of the Hawk ASIC. The Hawk adjusts system mapping to suit a given application via programmable map decoder registers. At system power-up or reset, a default processor memory map takes over.
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Memory maps Table 1-2. Default Processor Memory Map (Continued) Processor Address Size Start Definition End FEF9 0000 FEFE FFFF 384KB Not Mapped FEFF 0000 FEFF FFFF 64KB PCI Host Bridge (PHB) Registers FF00 0000 FFEF FFFF 15MB Not Mapped FFF0 0000 FFFF FFFF 1MB ROM/FLASH Bank A or Bank B (See Note) Note The first 1MB of ROM/FLASH Bank A (soldered Flash up to 8MB) appears in this range after a reset if the rom_b_rv control bit in the SMC’s ROM B Base/Size register is cleared.
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1 Product Data and Memory Maps Table 1-3. Suggested CHRP Memory Map Processor Address Start Size Definition Notes End 0000 0000 top_dram dram_size System Memory (onboard DRAM) 1 top_dram F3FF FFFF 4G-dram_size PCI Memory Space 1, 5 F400 0000 F7FF FFFF 64MB FLASH Bank A (optional) 1, 2 F800 0000 FBFF FFFF 64MB FLASH Bank B (optional) 1, 2 FC00 0000 FDFF FFFF 32MB Reserved FE00 0000 FE7F FFFF 8MB PCI/ISA I/O Space FE80 0000 FEF7 FFFF 7.
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Memory maps The following table shows the programmed values for the associated Hawk PCI Host Bridge Registers for the suggested Processor Memory Map. Table 1-4. Hawk PPC Register Values for Suggested Memory Map Address Register Name Register Name FEFF 0040 MSADD0 X000 F3FF [X:1..
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1 Product Data and Memory Maps PCI Local Bus Memory Map The PCI memory map is controlled by the MPU/PCI bus bridge controller portion of the Hawk ASIC and by the Universe PCI/VME bus bridge ASIC. The Hawk and Universe devices adjust system mapping to suit a given application via programmable map decoder registers. No default PCI memory map exists. Resetting the system turns the PCI map decoders off, and they must be reprogrammed in software for the intended application.
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System Bus Processors The MVME5100 has the BGA foot print that supports the MPC750, MPC755 and MPC7410 processors. The maximum external processor bus speed is 100 MHz. Parity checking is supported for the system address and data busses. Processor Type Identification The processor version can be determined by reading the Processor Version Register (PVR). The PVR version number value for the MPC750 and MPC755 processors is 0x0008.
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1 Product Data and Memory Maps checking may be disabled by programming Max accordingly. Refer to the MPC750, MPC755 or the MPC7410 RISC Microprocessor Users Manual and Chapter 3 of this manual for more information on programming cache. L2 Cache SRAM Size The L2 cache port will support SRAM configurations of 1MB or 2MB. The L2 cache size is defined by reading the Vital Product Data (VPD) SROM and programming the L2SIZ bits in the processor’s Cache Control Register (L2CR).
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System Bus ECC Memory The on-board and optional memory mezzanines allow a variety of memory size options; i.e., memory size can be 32MB, 64MB, 128MB, 256MB, or 512MB for a total of up to 1GB of planar and mezzanine ECC memory. The SDRAM memory is controlled by the Hawk ASIC, which provides single-bit error correction and double-digit error detection. ECC is calculated over 72-bits. Refer to the Hawk portion of this manual (Chapters 2 and 3) for additional programming information.
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1 Product Data and Memory Maps connector. The SBC mode (also know as 761 mode or IPMC mode) is backwards compatible with the MVME761 transition card and P2 adapter card (excluding PMC IO routing) used on MVME2600/2700 models. PMC mode is backwards compatible with the MVME2300 and MVME2400 models. The SBC mode is accomplished by configuring planar jumpers and attaching an IPMC761 PMC card in PMC slot 1 of the MVME5100.
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Hawk ASIC The Hawk ASIC also provides an Multi-Processor Interrupt Controller (MPIC) to handle various interrupt sources. The interrupt sources are: Four MPIC Timer Interrupts, the interrupts from all PCI devices, and the two software interrupts. Hawk I2C interface and configuration information The Hawk ASIC has an I2C (Inter-Integrated Circuit) two-wire serial interface bus: Serial Clock Line (SCL) and Serial Data Line (SDA) composed of two 256 x 8 Serial EEPROM’s.
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1 Product Data and Memory Maps to it. Other configuration information is needed by software to properly configure the Hawk’s control registers. This information can be obtained from devices connected to the I2C bus. Table 1-5.
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PCI Local Bus PCI Local Bus There are eight potential PCI bus masters on the MVME510x: ❏ Hawk ASIC (MPU/PCI bus bridge controller) ❏ Intel GD82559ER Ethernet controller (Port 1) ❏ Intel GD82559ER Ethernet controller (Port 2) ❏ Universe II ASIC (PCI/VME bus bridge controller) ❏ PMC Slot 1 (SCSI device on IPMC761 in PMC Slot 1) ❏ PIB device on IPMC761 in PMC Slot 1 ❏ PMC Slot 2 (PCI mezzanine card) ❏ PCI Expansion Slot PCI Arbitration Assignments for Hawk ASIC The PCI arbitration is performed
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1 Product Data and Memory Maps Table 1-6. PCI Arbitration Assignments (Continued) PCI Bus Request PCI Master(s) Request 3 (PARBI3) PMC Slot 2 Request 4 (PARBI4) PCIX Slot (PCI Expansion via PMCSPAN) Request 5 (PARBI5) Ethernet Port 1 (Front Panel) Request 6 (PARBI6) Ethernet Port 2 (Front Panel or P2) *Refer to the IPMC712/761 I/O Module Installation and Use manual.
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PCI Local Bus PMC/PCI Expansion Slots Up to two PMC slots and one PCIX slot may be present. The presence of the PMCs and/or PCIX can be positively determined by reading the Base Module Feature Register.
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1 Product Data and Memory Maps PROCESSOR VMEBUS PCI MEMORY ONBOARD MEMORY PROGRAMMABLE SPACE NOTE 2 NOTE 1 PCI MEMORY SPACE VME A24 VME A16 NOTE 3 VME A24 VME A16 NOTE 1 VME A24 PCI/ISA MEMORY SPACE VME A16 PCI I/O SPACE VME A24 VME A16 MPC RESOURCES NOTES: 1. Programmable mapping done by Hawk ASIC. 2. Programmable mapping performed via PCI Slave images in Universe ASIC. 3. Programmable mapping performed via Special Slave image (SLSI) in Universe ASIC. 11553.00 9609 Figure 1-2.
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PCI Local Bus PCI Configuration Space Access to PCI configuration space is accomplished via the Hawk ASIC using the CONADD and CONDAT Registers. The location and operation of these registers is fully described in the section titled Generating PCI Configuration Cycles in Chapter 2. The IDSEL assignments for MVME5100 are shown on the following table: Table 1-7.
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1 Product Data and Memory Maps The following table shows the current Vendor ID, the Device ID, and the Revision ID for each of the on-board PCI devices on the MVME5100: Table 1-8.
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PCI Local Bus Hawk External Register Bus Address Assignments This section will describe in detail the Hawk External Register Bus Address Assignments on MVME5100. The address range for the External Register Set on MVME5100 is fixed at $FEF88000-$FEF8FFFF. MVME5100 Hawk External Register Bus Summary The Hawk External Register Summary of the MVME5100 is shown in the table below: Table 1-9.
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1 Product Data and Memory Maps Table 1-9.
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PCI Local Bus Dual TL16C550 UARTs The MVME5100 implementation of the Dual TL16C550 UARTs are fully compliant with the PowerPlus II Programming Model for UART Registers. The following tables reflect this model. The MVME5100 uses UART-1 and UART-2 for asynchronous serial debug ports (four are allowed by the PowerPlus II Programming Model). The first UART (UART-1) is addressed at External Register Set Address Offset $8000 (FEF8 8000). The second (UART-2) is addressed at offset $8200 (FEF8 8200).
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Product Data and Memory Maps Status Register The MVME5100 implementation of this Register is fully compliant with the PowerPlus II programming model, with exceptions to bits RD5, RD6 and RD7, as identified in the following table: An 8-bit status register, accessible through the External Register Set port, defines the status of the Module. Table 1-11.
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PCI Local Bus MODFAIL Bit Register The MVME5100 implementation of this register is fully compliant with the PowerPlusII programming specification with exceptions to bit RD5, as indicated in the following table: The MODFAIL Bit Register provides the means to illuminate the module’s Board Fail LED. Table 1-12.
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Product Data and Memory Maps MODRST Bit Register The MODRST Bit register provides the means to reset the board. Table 1-13. MODRST Bit Register REG D0 D1 D2 D3 D4 D5 OPER R R R R R R R W RESET X X X X X X X 0 FIELD MODRST D6 D7 MODRST BIT Module Reset Bit Register - FEF880A0h RESET_REQ (Not Used 1 Setting this bit resets the module. This bit will automatically clear following the reset. This bit is undefined when reading.
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PCI Local Bus TBEN Bit Register The MVME5100 implementation of this register is fully compliant with the PowerPlus II Programming Specification, with exceptions to Bit RD6, as indicated in the following table: The TBEN Bit register provides the means to control the Processor Timebase Enable input. Table 1-14.
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1 Product Data and Memory Maps NVRAM/RTC & Watchdog Timer The MVME5100’s NVRAM/RTC and Watchdog Timer functions are supplied by an M48T37V device and is fully compliant with the PowerPlusII internal programming configuration. The M48T37V provides 32K of non-volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to the M48T37V is accomplished via three registers: the NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC Address Strobe 1 Register, and the NVRAM/RTC Data Port Register.
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PCI Local Bus Software Readable Header/Switch Register (S1) The MVME5100’s use of this register is fully compliant with the PowerPlus II internal programming configuration. A 1x8 header/switch (S1) is provided as the Software Readable Header/Switch (SRH). A logic 0 means the header/switch is in the "on" position for that particular bit and a logic 1 means the header/switch is in the "off" position.
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1 Product Data and Memory Maps Geographical Address Register (VME board) The following register provides geographical address status. The Geographical Address Register is an 8-bit read-only register.This register reflects the states of the geographical address pins on the 5-row, 160-pin P1 connector.
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PCI Local Bus Extended Features Register 1 This register is used to read if a PMC board is present or if a PCI expansion slot is present. Exceptions to the PowerPlus II Programming Specification are included in the following table. Table 1-16.
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Product Data and Memory Maps Board Last Reset Register This register is used to retain the source of the most recent reset. REG RD1 OPER R R R R R R R R RESET x x x x x x x x REQUIRED OR OPTIONAL X X O O O O O O 1-32 RD4 RD5 RD6 WDT2 FPBTN RD3 CPCIRST FIELD RD2 RD7 PWRON RD0 CMDRST BIT Board Last Reset Register - Offset 80F8h SWHRST 1 PWRON Power-On Reset. If set, a power-on reset has occurred or an undervoltage reset has occurred on 3.3V or 5V.
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PCI Local Bus Extended Features Register 2 This register is used to read if a PMC board is present or if a PCI expansion slot is present. Table 1-17. Extended Features Register 2 REG RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 FIELD PCIXP_L BIT Extended Features Register 2 - Offset 80F0h OPER R R R R R R R R RESET x x x x x x x x REQUIRED OR OPTIONAL O O O O O O O O PCIXP_L PCI Expansion Slot Present. If set, there is no PCIX device installed.
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1 Product Data and Memory Maps IPMC7xx ISA Bus Resources The following subsections provide resource information pertaining to ISA bus resources that are present, if an IPMC712 or IPMC761 is mounted on the MVME5x00 Series Computer. They are accessible through the W83C554 PIB, which is present on the IPMC module. W83C554 PIB Registers The PIB contains ISA Bridge I/O registers for various functions. These registers are actually accessible from the PCI bus. Refer to the W83C554 Data Book for details.
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IPMC7xx ISA Bus Resources Z85230 ESCC and Z8536 CIO Registers and Port Pins The Z85230 ESCC is used to provide the two sync/async serial ports on some MVME5100 series models. The PCLK which can be used to obtain the baud rates, is 10 MHz. Refer to the SCC User’s Manual for programming information on the Z85230 ESCC device.
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1 Product Data and Memory Maps Z8536 CIO Port Pins The assignment for the Port pins of the Z8536 CIO is as follows:: Table 1-20. Z8536 CIO Port Pins Assignment Port Pin Signal Name Direction Descriptions PA0 TM3_MID0 Input Port 3 Test Mode when IDREQ_ = 1; Module ID Bit 0 when IDREQ_ = 0. PA1 DSR3_MID1 Input Port 3 Data Set Ready when IDREQ_ = 1; Module ID Bit 1 when IDREQ_ = 0.
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IPMC7xx ISA Bus Resources Table 1-20. Z8536 CIO Port Pins Assignment (Continued) Port Pin Signal Name Direction Descriptions PB7 ABORT_ Input PC0 Reserved I/O Reserved PC1 Reserved I/O Reserved PC2 Reserved I/O Reserved PC3 Reserved I/O Note Status of ABORT# signal The direction and the polarity of the Z8536’s port pins are software programmable.
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1 Product Data and Memory Maps Table 1-21. Interpretation of MID3-MID0 IDREQ_ LLB3_ MODSEL MID3 MID2 MID1 MID0 Serial Module Type 0 1 0 0 1 1 Module 3: EIA530 DTE 0 1 1 1 1 1 Module 4 Not Installed Note 1-38 Module Assembly Number 01-W3879B01 Because IDREQ_ and MID3-MID0 signals go through the P2MX (P2 multiplexing) function used on MVME5100 series boards configured for the MVME761-type transition module, software must wait for the MID3-MID0 to become valid after asserting IDREQ_.
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IPMC7xx ISA Bus Resources ISA DMA Channels There are seven ISA DMA channels in the PIB. Channels 0 through 3 support only 8-bit DMA devices while Channels 5 through 7 support only 16-bit DMA devices. These DMA channels are assigned as follows: Table 1-22.
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2Hawk PCI Host Bridge & MultiProcessor Interrupt Controller 2 Introduction Overview This chapter describes the architecture and usage of the PowerPC to PCI Host Bridge (PHB) and the Multi-Processor Interrupt Controller (MPIC) portion of the Hawk ASIC. The Hawk is intended to provide PowerPC 60x (PPC60x bus) compliant devices access to devices residing on the PCI Local Bus. In the remainder of this chapter, the PPC60x bus is referred to as the PPC bus and the PCI Local Bus as PCI.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller – Read-ahead buffer for reads from the PPC bus. 2 – Four independent software programmable slave map decoders. ❏ Interrupt Controller – MPIC compliant. – MPIC programming model. – Support for 16 external interrupt sources and two processors. – Supports 15 programmable Interrupt and Processor Task priority levels. – Supports the connection of an external 8259 for ISA/AT compatibility. – Distributed interrupt delivery for external I/O interrupts.
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http://www.motorola.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Functional Description Architectural Overview A functional block diagram of the Hawk’s PCI Host Bridge (PHB) is shown in Figure 2-1. The PHB control logic is subdivided into the following functions: PCI Slave, PCI Master, PPC Slave and PPC Master. The PHB data path logic is subdivided into the following functions: PCI FIFO, PPC FIFO, PCI Input, PPC Input, PCI Output, and PPC Output.
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Functional Description All PCI originated PPC bound transactions utilize the PCI Slave and PPC Master functions for maintaining bus tracking and control. During both write and read transactions, the PCI Slave places command information into the PCI FIFO. The PPC Master draws this command information from the PCI FIFO when it is ready to process the transaction. During write transactions, write data is captured from the PCI bus within the PCI Input block. This data is fed into the PCI FIFO.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 PPC Address Mapping The PHB will map either PCI memory space or PCI I/O space into PPC address space using four programmable map decoders. These decoders provide windows of access to the PCI bus from the PPC bus. The most significant 16 bits of the PPC address are compared with the address range of each map decoder, and if the address falls within the specified range, the access is passed on to the PCI.
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Functional Description Each map decoder also includes a programmable 16-bit address offset. The offset is added to the 16 most significant bits of the PPC address, and the result is used as the PCI address. This offset allows PCI devices to reside at any PCI address, independent of the PPC address map. An example of this is shown in Figure 2-3. PPC Bus Address 8 0 8 0 1 2 3 4 0 1516 31 + XSOFFx Register 9 0 0 0 0 15 = PCI Bus Address 1 0 8 0 1 2 3 4 31 1615 0 Figure 2-3.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller AACK_ and TA_ allows the PPC Slave to assert a retry to the processor in the event that the transaction is unable to complete on the PCI side. It should be noted that any transaction that crosses a PCI word boundary could be disrupted after only having a portion of the data transferred. 2 The PPC Slave cannot perform compelled burst write transactions.
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Functional Description Table 2-1.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller For example, two burst transactions make the data FIFO the limiting factor for write posting. Four single beat transactions make the command FIFO the limiting factor. If either limit is exceeded, then any pending PPC transactions is delayed (AACK_ and TA_ are not asserted) until the PCI Master has completed a portion of the previously posted transactions and created some room within the command and/or data FIFOs.
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Functional Description 2 Table 2-2. PPC Master Transaction Profiles and Starting Offsets Start Offset (i.e. from 0x00,0x20,0x40,etc.) Write Profile Read Profile Notes 0x...00 -> 0x....07 Burst @ 0x00 Burst @ 0x20 .... Burst @ 0x00 Burst @ 0x20 .... Most efficient 0x....08 -> 0x....0f Single @ 0x08 Single @ 0x10 Single @ 0x18 Burst @ 0x20 .... Burst @ 0x00 Burst @ 0x20 .... Discard read beat 0x00 0x....10 -> 0x....17 Single @ 0x10 Single @ 0x18 Burst @ 0x20 .... Burst @ 0x00 Burst @ 0x20 ....
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller threshold should be lowered to anticipate any additional latencies incurred by the PPC Master on the PPC60x bus. Table 2-3 summarizes the PHB available write posting options. 2 Table 2-3.
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Functional Description Table 2-4.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PPC60x bus transfer types generated by the PPC Master depend on the PCI command code and the INV/GBL bits in the PSATTx registers. The GBL bit determines whether or not the GBL_ signal is asserted for all portions of a transaction and is fully independent of the PCI command code and INV bit. The following table shows the relationship between the PCI command codes and the INV bit. 2 Table 2-5.
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Functional Description PPC Arbiter 2 The PHB has an internal PPC60x bus arbiter. The use of this arbiter is optional. If the internal arbiter is disabled, then the PHB must be allowed to participate in an externally implemented PPC60x arbitration mechanism. The selection of either internal or external PPC arbitration mode is made by sampling an RD line at the release of reset. Refer to the section titled PHB Hardware Configuration in this chapter for more information.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller While RST_ is asserted, XARB0 through XARB4 is held in tri-state. If the internal arbiter mode is selected, then XARB0 through XARB3 is driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST_. If the external arbiter mode has been selected, then XARB4 is driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST_.
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Functional Description PPC Parity 2 The PHB generates data parity whenever it is sourcing PPC data. This happens during PPC Master write cycles and PPC Slave read cycles. Valid data parity is presented when DBB_ is asserted for PPC Master write cycles. Valid data parity is presented when TA_ is asserted for PPC Slave read cycles. The PHB checks data parity whenever it is sinking PPC data. This happens during PPC Master read cycles and PPC Slave write cycles.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 PPC Bus Timer The PPC Timer allows the current bus master to recover from a potential lock-up condition caused when there is no response to a transfer request. The time-out length of the bus timer is determined by the XBT field within the GCSR. The PPC Timer is designed to handle the case where an address tenure is not closed out by the assertion of AACK_.
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Functional Description be subject to a time-out period. During non-PCI bound cycles, the PPC Timer aborts the timing of the transaction any time it detects XTOCLM_ has been asserted. PCI Bus Interface The PCI Interface of the PHB is designed to connect directly to a PCI Local Bus and supports Master and Target transactions within Memory Space, I/O Space, and Configuration Space.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Bus Address Space 2 The PHB maps PPC address space into PCI Memory space using four programmable map decoders. The most significant 16 bits of the PCI address is compared with the address range of each map decoder, and if the address falls within the specified range, the access is passed on to the PPC bus. An example of this is shown in Figure 2-4.
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Functional Description Each map decoder also includes a programmable 16-bit address offset. The offset is added to the 16 most significant bits of the PCI address, and the result is used as the PPC address. This offset allows devices to reside at any PPC address, independent of the PCI address map. An example of this is shown in Figure 2-5. PCI Bus Address 8 0 8 0 1 2 3 4 31 1615 0 + PSOFFx Register 9 0 0 0 31 16 = PPC Bus Address 1 0 8 0 1 2 3 4 0 1516 31 Figure 2-5.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC Control Registers 2 The MPIC control registers are located within either PCI Memory or PCI I/O space using traditional PCI defined base registers within the predefined 64-byte header. Refer to the section titled Multi-Processor Interrupt Controller (MPIC) for more information. PCI Slave The PCI Slave provides the control logic needed to interface the PCI bus to the PCI FIFO.
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Functional Description Command Types: 2 Table 2-7 shows which types of PCI cycles the slave has been designed to accept. Table 2-7.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PCI Slave only honors the Linear Incrementing addressing mode. The PCI Slave performs a disconnect with data if any other mode of addressing is attempted. 2 Device Selection The PCI slave will always respond valid decoded cycles as a medium responder. Target Initiated Termination The PCI Slave normally strives to complete transactions without issuing disconnects or retries.
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Functional Description Fast Back-to-Back Transactions 2 The PCI Slave supports both of the fundamental target requirements for fast back-to-back transactions. The PCI Slave meets the first criteria of being able to successfully track the state of the PCI bus without the existence of an IDLE state between transactions. The second criteria associate with signal turn-around timing is met by default since the PCI Slave functions as a medium responder.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 PCI FIFO A 64-bit by 16 entry FIFO (4 cache lines total) is used to hold data between the PCI Slave and the PPC Master to ensure that optimum data throughput is maintained. The same FIFO is used for both read and write transactions. A 52-bit by 4 entry FIFO is used to hold command information being passed between the PCI Slave and the PPC Master.
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Functional Description It should be noted that even though the PCI Master can support burst transactions, a majority of the transaction types handled are single-beat transfers. Typically PCI space is not configured as cacheable, therefore burst transactions to PCI space would not naturally occur. It must be supported since it is conceivable that bursting could happen. For example, nothing prevents the processor from loading up a cache line with PCI write data and manually flushing the cache line.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-8. PCI Master Command Codes (Continued) 2 Entity Addressed PPC Transfer Type TBST* MEM -- Unsupported -PPC Mapped PCI Space Read 0 1 -- Unsupported -- C/BE PCI Command 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate Addressing The PCI Master generates all memory transactions using the Linear Incrementing addressing mode.
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Functional Description The PCI Master always removes its request when it receives a disconnect or a retry. There is a case where the PCI Master could assert a request but not actually perform a bus cycle. This may happen if the PCI Master is placed in the speculative request mode. Refer to the section titled PCI/PPC Contention Handling for more information. In no case will the PCI Master assert its request for more than 16 clocks without starting a transaction.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Memory and I/O Cycles 2 Each programmable slave may be configured to generate PCI I/O or memory accesses through the MEM and IOM fields in its XSATTx register as shown below. : MEM IOM PCI Cycle Type 1 x Memory 0 0 Contiguous I/O 0 1 Spread I/O If the MEM bit is set, the PHB performs Memory addressing on the PCI bus.
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Functional Description . 2 PPC Address + Offset 31 31 12 11 25 24 5 4 0 5 4 0 00 00 00 00 00 00 00 PCI Address 1915 9702 Figure 2-6. PCI Spread I/O Address Translation Spread I/O addressing allows each PCI device’s I/O registers to reside on a different PPC memory page, so device drivers can be protected from each other using memory page protection. All I/O accesses must be performed within natural word boundaries.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The second step is to either read or write configuration data into the CONFIG_DATA register. If the CONFIG_ADDRESS register is set up correctly, the PHB will pass this access on to the PCI bus as a configuration cycle. 2 The addresses of the CONFIG_ADDRESS and CONFIG_DATA registers are actually embedded within PCI I/O space.
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Functional Description The device that has its IDSEL connected to the address bit being asserted is selected for a configuration cycle. The PHB decodes the Device Number to determine which of the upper address lines to assert. The decoding of the five-bit Device Number is show as follows: Device Number Address Bit 00000 AD31 00001 - 01010 All Zeros 01011 AD11 01100 AD12 (etc.) (etc.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Interrupt Acknowledge Cycles 2 Performing a read from the PIACK register will initiate a single PCI Interrupt Acknowledge cycle. Any single byte or combination of bytes may be read from, and the actual byte enable pattern used during the read will be passed on to the PCI bus. Upon completion of the PCI interrupt acknowledge cycle, the PHB will present the resulting vector information obtained from the PCI bus as read data.
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Functional Description The Hawk’s PCI arbiter has various programming options. It supports 3 different priority schemes: fixed, round robin, and mixed mode. It also allows various levels of reprioritization programming options within fixed and mixed modes. Parking can be programmed to any of the requestors, the last requestor or none. A special bit is added to hold grant asserted for an agent that initiates a lock cycle.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When the arbiter is programmed for round robin priority mode, the arbiter maintains fairness and provides equal opportunity to the requestors by rotating its grants. The contents in “HEIR” field are “don’t cares” when operated in this mode. 2 When the arbiter is programmed for mixed mode, the 8 requestors are divided up into 4 groups and each groups is occupied by 2 requestors.
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Functional Description Notes 1. “000” is the default setting in mixed mode. 2 2. The HEIR setting only covers a small subset of all possible combinations and the requestors within each group is fixed and cannot be interchanged with other groups. It is the responsibility of the system designer to connect the request/grant pair in a manner most beneficial to their design goals. 3. All other combinations in the HEIR setting not specified in the table are invalid and should not be used.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Notes 1. “1000” is the default setting. 2 2. Parking disabled is a test mode only and should not be used, since no one will drive the PCI bus when in an idle state. 3. All other combinations in the PRK setting not specified in the table are invalid and should not be used. A special function is added to the PCI arbiter to hold the grant asserted through a lock cycle.
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Functional Description DL23-16 DL31-24 D6 D7 PPC Bus D7 D6 D5 D4 D3 D2 D1 D0 64-bit PCI 2 DL15-08 DL23-16 DL31-24 AD07-00 DL07-00 D3 D4 D5 D6 D7 D7 D6 D5 D4 32-bit PCI D3 D2 D1 D0 AD07-00 DH31-24 D2 AD15-08 DH23-16 D1 AD23-16 DH15-08 D0 AD31-24 DH07-00 AD15-08 DL15-08 D5 AD23-16 DL07-00 D4 AD31-24 DH31-24 D3 AD39-32 DH23-16 D2 AD47-40 DH15-08 D1 AD55-48 D0 AD63-56 DH07-00 . PPC Bus 1916 9610 Figure 2-7.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Address modification happens to the originating address regardless of whether the transaction originates from the PCI bus or the PPC bus. The three low order address bits are exclusive-ORed with a three-bit value that depends on the length of the operand, as shown in Table 2-13. 2 Table 2-13.
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Functional Description The CONFIG_ADDRESS and CONFIG_DATA registers are actually represented in PCI space to the processor and are subject to the Endian functions. For example, the powerup location of the CONFIG_ADDRESS register with respect to the PPC bus is $80000cf8 when the PHB is in BigEndian mode. When the PHB is switched to Little-Endian mode, the CONFIG_ADDRESS register with respect to the PPC bus is $80000cfc.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When any bit in the ESTAT is set, the PHB will attempt to latch as much information as possible about the error in the PPC Error Address (EADDR) and Attribute Registers (EATTR).
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Functional Description When not being loaded, the timer will continuously decrement itself until either reloaded by software or a count of zero is reached. If a timer reaches a count of zero, an output signal will be asserted and the count will remain at zero until reloaded by software or PHB reset is asserted. External logic can use the output signals of the timers to generate interrupts, machine checks, etc. Each timer is composed of a prescaler and a counter.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Table 2-14.
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Functional Description PPC1-Bug>md feff0000 FEFF0000 10574801 00030000 00A0FFF6 00000000 .W................ FEFF0010 000000BE 00000000 00000000 00000000 .................... PPC1-Bug>md feff0060 FEFF0060 000FFFFF 0000FFFF 000FFFFF 0000FFFF .................... FEFF0070 03FE0000 00000000 00000000 FFFFFFFF .................... PPC1-Bug>mw feff0068 55;b Effective address: FEFF0068 Effective data : 55 PPC1-Bug>md feff0060 FEFF0060 000FFFFF 0000FFFF 004FFFFF 0000FFFF ........O...........
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller A simultaneous indication of a stall from both slaves means that a bridge lock has happened. To resolve this, one of the slaves must back out of its currently pending transaction. This will allow the other stalled slave to proceed with its transaction. When the PCI Master detects bridge lock, it will always signal the PPC Slave to take actions to resolve the bridge lock.
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Functional Description From the perspective of the PCI bus, a better solution would be to select a PCI FIFO threshold that will allow the bridge lock resolution cycle to happen early enough to keep the PCI FIFO from getting filled. A similar case exists with regard to PCI read cycles. Having the bridge lock resolution associated with a particular PCI FIFO threshold would allow the PPC Master to get an early enough start at prefetching read data to keep the PCI Slave from starving for read data.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI speculative requesting will only be effective if the PCI arbiter will at least some times consider the PHB to be a higher priority master than the master performing the PPC60x bound write cycles. The PCI Master obeys the PCI specification for benign requests and will unconditionally remove a speculative request after 16 clocks. 2 The PHB considers the speculative PCI request mode to be the default mode of operation.
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Functional Description ❏ Write posted transactions originating from the processor bus are flushed by the nature of the FIFO architecture. The PHB will hold the processor with wait states until the PCI bound FIFO is empty. ❏ Write posted transactions originated from the PCI bus are flushed whenever the PCI slave has accepted a write-posted transaction and the transaction has not completed on the PPC bus.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller edge of CLK after RST_ has been released. All of the sampled pins are cascaded with several layers of registers to eliminate problems with hold time. 2 Table 2-15 summarizes the hardware configuration options that relate to the PHB. Table 2-15.
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Multi-Processor Interrupt Controller (MPIC) Multi-Processor Interrupt Controller (MPIC) 2 The MPIC is a multi-processor structured intelligent interrupt controller.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller If the OPIC bit (refer to the General Control-Status/Feature Registers section for more information) is enabled, the Hawk detected errors will be passed on to MPIC. If the OPIC bit is disabled, Hawk detected errors are passed directly to the processor 0 interrupt pin.
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Multi-Processor Interrupt Controller (MPIC) CSR’s Readability 2 Unless explicitly specified, all registers are readable and return the last value written. The exceptions are the IPI dispatch registers and the EOI registers which return zeros on reads, the interrupt source ACT bit which returns current interrupt source status, the interrupt acknowledge register, which returns the vector of the highest priority interrupt which is currently pending, and reserved bits which returns zeros.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Processor’s Current Task Priority Each processor has a task priority register which is set by system software to indicate the relative importance of the task running on that processor. The processor will not receive interrupts with a priority level equal to or lower than its current task priority. Therefore, setting the current task priority to 15 prohibits the delivery of all interrupts to the associated processor.
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Multi-Processor Interrupt Controller (MPIC) Interprocessor Interrupts (IPI) 2 Processors 0 and 1 can generate interrupts which are targeted for the other or both processors. There are four Interprocessor Interrupts (IPI) channels. The interrupts are initiated by writing a bit in the IPI dispatch registers. If subsequent IPI’s are initiated before the first is acknowledged, only one IPI will be generated. The IPI channels deliver interrupts in Direct Mode and can be directed to more than one processor.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Timers There is a divide by eight pre scaler which is synchronized to the PCI clock. The output of the pre scaler enables the decrement of the four timers. The timers may be used for system timing or to generate periodic interrupts. Each timer has four registers, which are used for configuration and control.
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Multi-Processor Interrupt Controller (MPIC) In the distributed delivery mode, the interrupt is pointed to one or more processors but it will be delivered to only one processor. Therefore, for externally sourced or I/O interrupts, multicast delivery is not supported.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Int. signals Program Visible Registers IPR Interrupt Selector_1 Interrupt Selector_0 IRR_1 IRR_0 ISR_1 ISR_0 Interrupt Router INT 1 INT 0 Figure 2-9.
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Multi-Processor Interrupt Controller (MPIC) Program Visible Registers 2 These are the registers that software can access. They are described in detail in the MPIC Registers section. Interrupt Pending Register (IPR) The interrupt signals to MPIC are qualified and synchronized to the clock by the IPR. If the interrupt source is internal to the Hawk ASIC or external with their Sense bit = 0 (edge sensitive), a bit is set in the IPR.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Interrupt Request Register (IRR) There is a Interrupt Request Register (IRR) for each processor. The IRR always passes the output of the IS except during Interrupt Acknowledge cycles. This guarantees that the vector which is read from the Interrupt Acknowledge Register does not change due to the arrival of a higher priority interrupt. The IRR also serves as a pipeline register for the two tick propagation time through the IS.
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Multi-Processor Interrupt Controller (MPIC) Then one of these bits is delivered to each Interrupt Selector. Since this interrupt source can be multicast, each of these IPR bits must be cleared separately when the vector is returned for that interrupt to a particular processor. If one of the following sets of conditions is true, the interrupt pin for processor 0 is driven active. ❏ Set1 – The source ID in IRR_0 is from an external source. – The destination bit for processor 1 is 0 for this interrupt.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Programming Notes External Interrupt Service The following summarizes how an external interrupt is serviced: 2-62 ❏ An external interrupt occurs. ❏ The processor state is saved in the machine status save/restore registers. A new value is loaded into the Machine State Register (MSR). The External Interrupt Enable bit in the new MSR (MSRee) is set to zero. Control is transferred to the O/S external interrupt handler.
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Multi-Processor Interrupt Controller (MPIC) – The device driver interrupt service routine associated with this interrupt vector is invoked. – If the interrupt source was not the 8259, the interrupt handler issues an EOI request for this interrupt vector to the MPIC. If the interrupt source was the 8259 and any of the nested interrupt modes of the 8259 are enabled, the interrupt handler issues an EOI request to the 8259. Normally, interrupts from ISA devices are connected to the 8259 interrupt controller.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Operation Interprocessor Interrupts Four interprocessor interrupt (IPI) channels are provided for use by all processors. During system initialization the IPI vector/priority registers for each channel should be programmed to set the priority and vector returned for each IPI event. During system operation a processor may generate an IPI by writing a destination mask to one of the IPI dispatch registers.
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Multi-Processor Interrupt Controller (MPIC) EOI Register 2 Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event. If multiple nested interrupts are in service, the EOI command terminates the interrupt service of the highest priority source. Once an interrupt is acknowledged, only sources of higher priority will be allowed to interrupt the processor until the EOI command is received.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Architectural Notes The hardware and software overhead required to update the task priority register synchronously with instruction execution may far outweigh the anticipated benefits of the task priority register. To minimize this overhead, the interrupt controller architecture should allow the task priority register to be updated asynchronously with respect to instruction execution.
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Registers Registers 2 This section provides a detailed description of all PHB registers. The section is divided into two parts: the first covers the PPC Registers and the second covers the PCI Configuration Registers. The PPC Registers are accessible only from the PPC bus using any single beat valid transfer size. The PCI Configuration Registers reside in PCI configuration space. These are primarily accessible from the PPC bus by using the CONFIG_ADDRESS and CONFIG_DATA registers.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 PPC Registers The PPC register map of the PHB is shown in Table 2-16. Table 2-16.
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Registers Table 2-16.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Vendor ID/Device ID Registers Address Bit $FEFF0000 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 Name VENID DEVID R R $1057 $4803 Operation Reset VENID Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola and is hardwired as a read-only value.
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Registers General Control-Status/Feature Registers 2 The General Control-Status Register (GCSR) provides miscellaneous control and status information for the PHB.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 XFBR PPC Flush Before Read. If set, the PHB will guarantee that all PCI initiated posted write transactions will be completed before any PPC-initiated read transactions will be allowed to complete. When XFBR is clear, there is no correlation between these transaction types and their order of completion. Refer to the section titled Transaction Ordering for more information. XBTx PPC Bus Time-out.
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Registers PPC Arbiter/PCI Arbiter Control Registers 2 The PPC Arbiter Register (XARB) provides control and status for the PPC Arbiter. Refer to the section titled PPC Arbiter for more information.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 PRI Priority. If set, the PPC Arbiter will impose a rotating between CPU0 grants. If cleared, a fixed priority will be established between CPU0 and CPU1 grants, with CPU0 having a higher priority than CPU1. PRKx Parking. This field determines how the PPC Arbiter will implement CPU parking. The encoding of this field is shown in the table below.
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Registers PRKx HIERx HIER Parking. This field is used by the PCI Arbiter to establish a particular bus parking scheme. The encoding of this field is shown in the following table. PRK Parking Scheme 0000 Park on last master 0001 Park always on PARB6 0010 Park always on PARB5 0011 Park always on PARB4 0100 Park always on PARB3 0101 Park always on PARB2 0110 Park always on PARB1 0111 Park always on PARB0 1000 Park always on HAWK 1111 None Hierarchy.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When using the mixed priority scheme, the encoding of this field is shown in the following table. 2 HIER 2-76 Priority ordering, highest to lowest 000 Group 1 -> Group 2 -> Group 3 -> Group 4 001 Group 4 -> Group 1 -> Group 2 -» Group 3 010 Group 3 -> Group 4 -> Group 1 -> Group 2 011 Group 2 -> Group 3 -> Group 4 -> Group 1 100 Reserved 101 Reserved 110 Reserved 111 Reserved POL Park on lock.
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Registers Hardware Control-Status/Prescaler Adjust Register 2 The Hardware Control-Status Register (HCSR) provides hardware specific control and status information for the PHB.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller WLRTx 2 WLRT 00 01 10 11 Write lock resolution threshold Match write threshold mode (i.e. PSATTx WXFT) Immediate FIFO full FIFO full RLRTx RLRT 00 01 10 11 Write Lock Resolution Threshold. This field is used by the PHB to determine a PPC bound write FIFO threshold at which a bridge lock resolution will create a retry on a pending PCI bound transaction. The encoding of this field is shown in the following table.
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Registers PPC Error Test/Error Enable Register 2 The Error Test Register (ETEST) provides you with a way to send certain types of errors to test the PHB error capture and status circuitry.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 2-80 DFLT Default PPC Master ID. This bit determines which MCHK_ pin will be asserted for error conditions in which the PPC Master ID cannot be determined or the PHB was the PPC Master. For example, in the event of a PCI parity error for a transaction in which the PHB’s PCI Master was not involved, the PPC Master ID cannot be determined. When DFLT is set, MCHK1_ is used. When DFLT is clear, MCHK0_ will be used.
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Registers XBTOI PPC Address Bus Time-out Interrupt Enable. When this bit is set, the XBTO bit in the MERST register will be used to assert an interrupt through the MPIC interrupt controller. When this bit is clear, no interrupt will be asserted. XDPEI PPC Data Parity Error Interrupt Enable. When this bit is set, the XDPE bit in the ESTAT register will be used to assert an interrupt through the MPIC. When this bit is clear, no interrupt will be asserted. PPERI PCI Parity Error Interrupt Enable.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 PPC Error Status Register The Error Status Register (ESTAT) provides an array of status bits pertaining to the various errors that the PHB can detect. The bits within the ESTAT are defined in the following paragraphs.
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Registers PPER PCI Parity Error. This bit is set when the PCI PERR_ pin is asserted. It may be cleared by writing it to a 1; writing it to a 0 has no effect. When the PPERM bit in the EENAB register is set, the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the EATTR register. When the PPERI bit in the EENAB register is set, the assertion of this bit will assert an interrupt through the MPIC. PSER PCI System Error. This bit is set when the PCI SERR_ pin is asserted.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 PPC Error Address Register The Error Address Register (EADDR) captures addressing information on the various errors that the PHB can detect. The register captures the PPC address when the XBTO bit is set in the ESTAT register. The register captures the PCI address when the PSMA or PRTA bits are set in the ESTAT register. The register’s contents are not defined when the XDPE, PPER or PSER bits are set in the ESTAT register.
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Registers PPC Error Attribute Register 2 The Error Attribute Register (EATTR) captures attribute information on the various errors that the PHB can detect. If the XDPE, PPER or PSER bits are set in the ESTAT register, the contents of the EATTR register are zero.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller If the PSMA or PRTA bit are set, the register is defined by the following table: 2 Address Bit $FEFF002C 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 Name EATTR $00 $00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2-86 R R R R R R R R R R R R R R R R R Reset R BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 COMM0 COMM1 COMM2 COMM3 MID0 MID1 WP Operation WP Write Post Completion.
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Registers PCI Interrupt Acknowledge Register 2 The PCI Interrupt Acknowledge Register (PIACK) is a read only register that is used to initiate a single PCI Interrupt Acknowledge cycle. Any single byte or combination of bytes may be read from, and the actual byte enable pattern used during the read will be passed on to the PCI bus. Upon completion of the PCI interrupt acknowledge cycle, the PHB will present the resulting vector information obtained from the PCI bus as read data.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Slave Address (0,1 and 2) Registers The PPC Slave Address Registers (XSADD0, XSADD1, and XSADD2) contains address information associated with the mapping of PPC memory space to PCI memory I/O space.
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Registers PPC Slave Offset/Attribute (0, 1 and 2) Registers XSATTx R R/W R/W R R/W R R R/W R/W Reset R/W $0000 $00 0 0 0 0 0 0 0 0 Operation MEM IOM XSOFFx REN WEN Name WPEN Bit XSOFF0/XSATT0 - $FEFF0044 XSOFF1/XSATT1 - $FEFF004C XSOFF2/XSATT2 - $FEFF0054 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 2 The PPC Slave Offset Registers (XSOFF0, XSOFF1, and XSOFF2) contains offset information associated with the mapping of PPC memory space to PCI
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 MEM PCI Memory Cycle. If set, the corresponding PPC Slave will generate transfers to or from PCI memory space. When clear, the corresponding PPC Slave will generate transfers to or from PCI I/O space using the addressing mode defined by the IOM field. IOM PCI I/O Mode. If set, the corresponding PPC Slave will generate PCI I/O cycles using spread addressing as defined in the section titled Generating PCI Cycles.
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Registers The fields within XSADD3 are defined as follows: 2 START Start Address. This field determines the start address of a particular memory area on the PPC bus which will be used to access PCI bus resources. The value of this field will be compared with the upper 16 bits of the incoming PPC address. END End Address. This field determines the end address of a particular memory area on the PPC bus which will be used to access PCI bus resources.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PPC Slave Attributes Register 3 (XSATT3) contains attribute information associated with the mapping of PPC memory space to PCI I/O space. The bits within the XSATT3 register are defined as follows: 2 REN Read Enable. If set, the corresponding PPC Slave is enabled for read transactions. WEN Write Enable. If set, the corresponding PPC Slave is enabled for write transactions. WPEN Write Post Enable.
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Registers KEY Key. This field is used during the two step arming process of the Control register. This field is sensitive to the following data patterns: PATTERN_1 = $55 PATTERN_2 = $AA The Control register will be in the armed state if PATTERN_1 is written to the KEY field. The Control register will be changed if in the armed state and PATTERN_2 is written to the KEY field. An incorrect sequence of patterns will cause the Control register to be in the unarmed state.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller RES Timer Resolution Approximate Max Time 0100 16 us 1 sec 0101 32 us 2 sec 0110 64 us 4 sec 0111 128 us 8 sec 1000 256 us 16 sec 1001 512 us 32 sec 1010 1024 us 1 min 1011 2048 us 2 min 1100 4096 us 4 min 1101 8192 us 8 min 1110 16,384 us 16 min 1111 32,768 us 32 min 2 RELOAD Reload. This field is written with a value that will be used to reload the timer.
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Registers PPC6-Bug>mw feff0068 aa88;h Effective address: FEFF0068 Effective data : AA88 PPC6-Bug>md feff006c FEFF006C 0000B26D 03FE4000 00000000 00000000 ...m..@.......... FEFF007C FFFFFFFE FFFFFFFF FFFFFFFF FFFFFFFF ................. PPC6-Bug>md feff006c FEFF006C 00006145 03FE4000 00000000 00000000 ..aE..@.......... FEFF007C FFFFFFFE FFFFFFFF FFFFFFFF FFFFFFFF ................. PPC6-Bug>md feff0068 FEFF0068 0088FFFF 00000000 03FE4000 00000000 ...........@.....
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller WDTxSTAT Registers Address Bit WDT1STAT - $FEFF0064 WDT2STAT - $FEFF006C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 2 WDTxSTAT Name Operation Reset COUNT R R R $00 $00 $FF The Watchdog Timer Status Registers (WDT1STAT and WDT2STAT) are used to provide status information from the watchdog timer functions within the PHB. The field within WDTxSTAT registers is defined as follows: COUNT Count.
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Registers PCI Registers 2 The PCI Configuration Registers are compliant with the configuration register set described in the PCI Local Bus Specification, Revision 2.1. The CONFIG_ADDRESS and CONFIG_DATA registers described in this section are accessed from the PPC bus within PCI I/O space. All write operations to reserved registers will be treated as no-ops. That is, the access will be completed normally on the bus and the data will be discarded.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Table 2-18. PCI I/O Register 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 <--- Bit CONFIG_ADDRESS $CF8 CONFIG_DATA $CFC Vendor ID/ Device ID Registers Offset Bit Name $00 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 DEVID VENID R R $4803 $1057 Operation Reset 2-98 VENID Vendor ID.
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Registers PCI Command/ Status Registers 2 The Command Register (COMMAND) provides coarse control over the PHB ability to generate and respond to PCI cycles.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The Status Register (STATUS) is used to record information for PCI bus related events. The bits within the STATUS register are defined as follows: 2 2-100 P66M PCI66 MHz. This bit indicates the PHB is capable of supporting a 66.67 MHz PCI bus. FAST Fast Back-to-Back Capable. This bit indicates that the PHB is capable of accepting fast back-to-back transactions with different targets. DPAR Data Parity Detected.
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Registers Revision ID/ Class Code Registers 2 Offset Bit $08 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Operation Reset CLASS REVID R R $060000 $01 REVID Revision ID. This register identifies the PHB revision level. This register is duplicated in the PPC Registers. CLASS Class Code.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 MPIC I/O Base Address Register Offset Bit $10 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name MIBAR Operation Reset R/W R $0000 $0000 IO/MEM R 1 RES R 0 BASE The MPIC I/O Base Address Register (MIBAR) controls the mapping of the MPIC control registers in PCI I/O space. IO/MEM IO Space Indicator. This bit is hard-wired to a logic one to indicate PCI I/O space.
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Registers The MPIC Memory Base Address Register (MMBAR) controls the mapping of the MPIC control registers in PCI memory space. 2 IO/MEM IO Space Indicator. This bit is hard-wired to a logic zero to indicate PCI memory space. MTYPx Memory Type. These bits are hard-wired to zero to indicate that the MPIC registers can be located anywhere in the 32-bit address space. PRE Prefetch. This bit is hard-wired to zero to indicate that the MPIC registers are not prefetchable. BASE Base Address.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PCI Slave Address Registers (PSADDx) contain address information associated with the mapping of PCI memory space to PPC memory space. The fields within the PSADDx registers are defined as follows: 2 START Start Address. This field determines the start address of a particular memory area on the PCI bus which will be used to access PPC bus resources. The value of this field will be compared with the upper 16 bits of the incoming PCI address.
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Registers INV Invalidate Enable. If set, the PPC Master will issue a transfer type code which specifies the current transaction should cause an invalidate for each PPC transaction originated by the corresponding PCI Slave. The transfer type codes generated are shown in Table 2-5 on page 2-14. GBL Global Enable. If set, the PPC Master will assert the GBL_ pin for each PPC transaction originated by the corresponding PCI Slave. RAEN Read Ahead Enable.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller will be four cache lines. This field is only applicable if read-ahead has been enabled. The encoding of this field is shown in the table above. 2 WXFT Write FIFO Threshold 00 4 Cache lines 01 3 Cache lines 10 2 Cache lines 11 1 Cache lines WXFTx Write Any FIFO Threshold. This field is used by the PHB to determine a FIFO threshold at which to start writing data into local memory during any PCI write transaction.
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Registers Conceptual perspective from the PCI bus: Offset Bit $CFB $CFA $CF8 CONFIG_ADDRESS FUN REG R/W R R/W R/W R/W R/W 1 $00 $00 $00 $0 $00 0 0 DEV R R BUS EN Reset $CF9 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Operation 2 Perspective from the PPC bus in Big Endian mode: Offset Bit (DH) $CF8 $CF9 $CFA $CFB 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The register fields are defined as follows: 2 REG Register Number. Configuration Cycles: Identifies a target double word within a target’s configuration space. This field is copied to the PCI AD bus during the address phase of a Configuration cycle. Special Cycles: This field must be written with all zeros. FUN Function Number. Configuration Cycles: Identifies a function number within a target’s configuration space.
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Registers CONFIG_DATA Register The description of the CONFIG_DATA register is also presented in three perspectives; from the PCI bus, from the PPC bus in Big Endian mode, and from the PPC bus in Little Endian mode. Note that the view from the PCI bus is purely conceptual, since there is no way to access the CONFIG_DATA register from the PCI bus.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 MPIC Registers The following conventions are used in the Hawk register charts: ❏ R - Read Only field. ❏ R/W - Read/Write field. ❏ S - Writing a ONE to this field sets this field. ❏ C - Writing a ONE to this field clears this field. MPIC Registers The MPIC register map is shown in Table 2-19. The "Off" field is the address offset from the base address of the MPIC registers in the PPC-IO or PPC-Memory space.
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Registers Table 2-19.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-19. MPIC Register Map (Continued) 2 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 Off 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2-112 INT. SRC. 5 VECTOR-PRIORITY REGISTER $100a0 INT. SRC. 5 DESTINATION REGISTER $100b0 INT. SRC. 6 VECTOR-PRIORITY REGISTER $100c0 INT. SRC. 6 DESTINATION REGISTER $100d0 INT. SRC. 7 VECTOR-PRIORITY REGISTER $100e0 INT. SRC. 7 DESTINATION REGISTER $100f0 INT. SRC.
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Registers Table 2-19. MPIC Register Map (Continued) 2 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 Off 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 IPI 3 DISPATCH REGISTER PROC. 0 $20070 CURRENT TASK PRIORITY REGISTER PROC. 0 $20080 IACK REGISTER P0 $200a0 EOI REGISTER P0 $200b0 IPI 0 DISPATCH REGISTER PROC. 1 $21040 IPI 1 DISPATCH REGISTER PROC. 1 $21050 IPI 2 DISPATCH REGISTER PROC. 1 $21060 IPI 3 DISPATCH REGISTER PROC. 1 $21070 CURRENT TASK PRIORITY REGISTER PROC.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 NIRQ NUMBER OF IRQs. The number of the highest external IRQ source supported. The IPI, Timer, and PHB Detected Error interrupts are excluded from this count. NCPU NUMBER OF CPUs. The number of the highest physical CPU supported. There are two CPUs supported by this design. CPU #0 and CPU #1. VID VERSION ID. Version ID for this interrupt controller. This value reports what level of the specification is supported by this implementation.
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Registers M CASCADE MODE. Allows cascading of an external 8259 pair connected to the first interrupt source input pin (0). In the pass through mode, interrupt source 0 is passed directly through to the processor 0 INT pin. MPIC is essentially disabled. In the mixed mode, 8259 interrupts are delivered using the priority and distribution mechanism of the MPIC. The Vector/Priority and Destination registers for interrupt source 0 are used to control the delivery mode for all 8259 generated interrupt sources.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Vendor Identification Register Offset Bit $01080 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name VENDOR IDENTIFICATION STP Operation Reset R R R R $00 $00 $00 $00 There are two fields in the Vendor Identification Register which are not defined for the MPIC implementation but are defined in the MPIC specification.
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Registers IPI Vector/Priority Registers 2 Offset Bit IPI 0 - $010A0 IPI 1 - $010B0 IPI 2 - $010C0 IPI 3 - $010D0 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Reset PRIOR ACT R 0 MASK R/W 1 Operation IPI VECTOR/PRIORITY VECTOR R R/W R R/W $000 $0 $00 $00 MASK MASK. Setting this bit disables any further interrupts from this source.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Spurious Vector Register Offset Bit $010E0 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Operation Reset VECTOR R R R R/W $00 $00 $00 $FF VECTOR This vector is returned when the Interrupt Acknowledge register is read during a spurious vector fetch.
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Registers Timer Current Count Registers 2 Offset Bit Timer 0 - $01100 Timer 1 - $01140 Timer 2 - $01180 Timer 3 - $011C0 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Reset CC T R 0 Operation TIMER CURRENT COUNT R $00000000 T TOGGLE. This bit toggles whenever the current count decrements to zero.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Timer Basecount Registers Offset Bit Timer 0 - $01110 Timer 1 - $01150 Timer 2 - $01190 Timer 3 - $011D0 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Reset 2-120 BC CI R/W 1 Operation TIMER BASECOUNT R/W $00000000 CI COUNT INHIBIT. Setting this bit to one inhibits counting for this timer. Setting this bit to zero allows counting to proceed. BC BASE COUNT.
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Registers Timer Vector/Priority Registers 2 Offset Bit Timer 0 - $01120 Timer 1 - $01160 Timer 2 - $011A0 Timer 3 - $011E0 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Reset PRIOR ACT R 0 MASK R/W 1 Operation TIMER VECTOR/PRIORITY VECTOR R R/W R R/W $000 $0 $00 $00 MASK MASK. Setting this bit disables any further interrupts from this source.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Timer Destination Registers Offset Bit Timer 0 - $01130 Timer 1 - $01170 Timer 2 - $011B0 Timer 3 - $011F0 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name TIMER DESTINATION Reset R R R R $00 $00 $00 $00 P0 R/W 0 P1 R/W 0 Operation This register indicates the destinations for this timer’s interrupts. Timer interrupts operate in the Directed delivery interrupt mode.
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Registers MASK MASK. Setting this bit disables any further interrupts from this source. If the mask bit is cleared while the bit associated with this interrupt is set in the IPR, the interrupt request will be generated. ACT ACTIVITY. The activity bit indicates that an interrupt has been requested or that it is in-service. The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In-Service Register is set. POL POLARITY. This bit sets the polarity for external interrupts.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 External Source Destination Registers Offset Bit Int Src 0 - $10010 Int Src 1-> Int Src 15 - $10030 -> $101F0 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Reset R R R R $00 $00 $00 $00 P0 R/W 0 P1 R/W 0 Operation EXTERNAL SOURCE DESTINATION This register indicates the possible destinations for the external interrupt sources.
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Registers Hawk Internal Error Interrupt Vector/Priority Register Offset Bit $10200 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name HAWK INTERNAL ERROR INTERRUPT VECTOR/PRIORITY $000 PRIOR R/W R R/W 0 0 1 0 R 0 R/W 1 Reset R R R SENSE R R ACT MASK Operation 2 VECTOR $0 $00 $00 MASK MASK. Setting this bit disables any further interrupts from this source.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 Hawk Internal Error Interrupt Destination Register Offset Bit $10210 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Reset R R R R $00 $00 $00 $00 P0 R/W 0 P1 R/W 0 Operation HAWK INTERNAL ERROR INTERRUPT DESTINATION This register indicates the possible destinations for the Hawk internal error interrupt source.
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Registers Current Task Priority Registers 2 Offset Bit Processor 0 $20080 Processor 1 $21080 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name CURRENT TASK PRIORITY TP Operation Reset R R R R R/W $00 $00 $00 $0 $F There is one Task Priority Register per processor. Priority levels from 0 (lowest) to 15 (highest) are supported. Setting the Task Priority Register to 15 masks all interrupts to this processor.
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 2 End-of-Interrupt Registers Offset Bit Processor 0 $200B0 Processor 1 $210B0 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name Operation Reset EOI R R R R W $00 $00 $00 $0 $0 EOI 2-128 END OF INTERRUPT. There is one EOI register per processor. EOI Code values other than 0 are currently undefined. Data values written to this register are ignored; zero is assumed.
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3System Memory Controller (SMC) 3 Introduction The SMC in the Hawk ASIC is equivalent to the former Falcon Pair portion of a Falcon/Raven chipset. The SMC has interfaces between the PPC60x bus and SDRAM, ROM/Flash, and its Control and Status Register sets (CSR). Note that the term SDRAM refers to Synchronous Dynamic Random Access Memory and is used throughout this document. Overview This chapter provides a functional description and programming model for the SMC portion of the Hawk.
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System Memory Controller (SMC) ❏ ROM/Flash Interface – Two blocks with each block being 16 or 64 bits wide. – Programmable access time on a per-block basis. 3 ❏ I2C master interface. ❏ External status/control register support Block Diagrams Figure 3-1 depicts a Hawk as it would be connected with SDRAMs in a system. Figure 3-2 shows the SMC’s internal data paths. Figure 3-3 shows the overall SDRAM connections. Figure 3-4 shows a block diagram of the SMC portion of the Hawk ASIC.
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Block Diagrams SDRAM Side HAMGEN 3 (8 Bits) Latched D (64 Bits) MUX DFF’s PowerPC Side D[0:63] (64 Bits) (8 Bits) + Uncorrected Data (64 Bits) CKD[0:7] PARGEN DP[0:7] LATCHES + RD[0:63] (8 Bits) HAMGEN SYNDEC (8 Bits) LATCHES Corrected Data (64 Bits) PARCHK (64 Bits) Figure 3-2. Hawk’s System Memory Controller Internal Data Paths http://www.motorola.
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System Memory Controller (SMC) 3 D0/D1_CS_ C0/C1_CS_ B0/B1_CS_ A0/A1_CS_ BA,RA,RAS_, HAWK CAS_,WE_,DQM RD0-63 CKD0-7 SDRAM BLOCK A SDRAM BLOCK B SDRAM BLOCK C SDRAM BLOCK D Figure 3-3.
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Block Diagrams 3 PPC60x Ctrl SDRAM & ROM/Flash CONTROL PPC60x SLAVE INTERFACE PPC60x Attr PPC60x ADDRESS DECODER REFRESHER /SCRUBBER ARBITER MEM Ctrl SDRAM ADDRESS MULTIPLEXOR MEM Addr PPC60x Addr I2C Bus PPC60x Data I2C INTERFACE STATUS /CONTROL REGISTERS DATA MULTIPLEXOR SDRAM ERROR LOGGER JTAG MEM Data Figure 3-4. Hawk’s System Memory Controller Block Diagram http://www.motorola.
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System Memory Controller (SMC) Functional Description The following sections describe the logical function of the SMC. The SMC has interfaces between the PowerPC bus and SDRAM, ROM/Flash, and its Control and Status Register sets (CSR). 3 SDRAM Accesses Four-beat Reads/Writes The SMC performs best when doing bursting (4-beat accesses). This is made possible by the burst nature of synchronous DRAMs.
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Functional Description Page Holding Further savings comes when the new address is close enough to a previous one that it falls within an open page in the SDRAM array. When this happens, the SMC can transfer the data for the next cycle without having to wait to activate a new page in SDRAM. In the SMC this feature is referred to as page holding. SDRAM Speeds The SDRAM that the Hawk ASIC controls use the 60x clock.
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System Memory Controller (SMC) Table 3-1. 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 SDRAMs (CAS_latency of 2) (Continued) 3 Access Type 4-Beat Write after 4-Beat Write, SDRAM Bank Active - Page Hit Access Time Comments 3-1-1-1 3-1-1-1 for the second burst write after idle. 2-1-1-1 for subsequent burst writes.
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Functional Description SDRAM Organization The SDRAM is organized as 1, 2, 3, 4, 5, 6, 7, or 8 blocks, 72 bits wide with 64 of the bits being normal data and the other 8 being checkbits. The 72 bits of SDRAM for each block can be made up of x4, x8, or x16 components or of 72-bit DIMMs that are made up of x4 or x8 components. The 72-bit, unbuffered DIMMs can be used as long as AC timing is met and they use the components listed. All components must be organized with 4 internal banks.
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System Memory Controller (SMC) PPC60x Data Parity The Hawk has 8 DP pins for generating and checking PPC60x data bus parity. 3 During read cycles that access the SMC, the Hawk generates the correct value on DP0-DP7 so that each data byte lane along with its corresponding DP signal has odd parity. This can be changed on a lane basis to even parity by software bits that can force the generation of wrong (even) parity.
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Functional Description Cache Coherency The SMC supports cache coherency to SDRAM only. It does this by monitoring the ARTRY_ control signal on the PPC60x bus and behaving appropriately when it is asserted. When ARTRY_ is asserted, if the access is a SDRAM read, the SMC does not source the data for that access. If the access is a SDRAM write, the SMC does not write the data for that access. Depending upon when the retry occurs, the SMC may cycle the SDRAM even though the data transfer does not happen.
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System Memory Controller (SMC) Error Reporting The SMC checks data from the SDRAM during single- and four-beat reads, during single-beat writes, and during scrubs. Table 3-2 shows the actions it takes for different errors during these accesses 60x. 3 Note that the SMC does not assert TEA_ on double-bit errors. In fact, the SMC does not have a TEA_ signal pin and it assumes that the system does not implement TEA_. The SMC can, however, assert machine check (MCHK0_) on double-bit error. Table 3-2.
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Functional Description Notes 1. No opportunity for error since no read of SDRAM occurs during a four-beat write. 2. The SMC asserts Hawk’s internal error interrupt output upon detecting an interrupt-qualified error condition. The potential sources of Hawk’s internal error interrupt assertion are single-bit error, multiple-bit error, and single-bit error counter overflow. Error Logging ECC error logging is facilitated by the SMC because of its internal latches.
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System Memory Controller (SMC) ROM/Flash Interface The SMC provides the interface for two blocks of ROM/Flash. Each block provides addressing and control for up to 64MB. Note that no ECC error checking is provided for the ROM/Flash. 3 The ROM/Flash interface allows each block to be individually configured by jumpers and/or by software as follows: 1. Access for each block is controlled by three software programmable control register bits: an overall enable, a write enable, and a reset vector enable.
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Functional Description When the width status bit is cleared, the block’s ROM /Flash is considered to be 16 bits wide, where each half of the SMC interfaces to 8 bits. In this mode, the following rules are enforced: a. only single-byte writes are allowed (all other sizes are ignored), and b. all reads are allowed (multiple accesses are performed to the ROM/Flash devices when the read is for greater than one byte).
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System Memory Controller (SMC) Table 3-3.
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Functional Description Table 3-4.
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System Memory Controller (SMC) Table 3-4.
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Functional Description ROM/Flash Speeds The SMC provides the interface for two blocks of ROM/Flash. Access times to ROM/Flash are programmable for each block. Access times are also affected by block width. Refer to Table 3-5, Table 3-6, Table 3-7, and Table 3-8 for specific timing numbers. Table 3-5.
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System Memory Controller (SMC) Table 3-6.
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Functional Description Note The information in Table 3-7 applies to access timing when configured for devices with an access time equal to 5 clock periods. 3 Table 3-8.
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System Memory Controller (SMC) I2C Interface The ASIC has an I2C (Inter-Integrated Circuit) two-wire serial interface bus: Serial Clock Line (SCL) and Serial Data Line (SDA). This interface has master-only capability and may be used to communicate the configuration information to a slave I2C device such as serial EEPROM. The I2C interface is compatible with these devices, and the inclusion of a serial EEPROM in the memory subsystem may be desirable.
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Functional Description I2C Byte Write The I2C Status Register contains the i2_cmplt bit which is used to indicate if the I2C master controller is ready to perform an operation. Therefore, the first step in the programming sequence should be to test the i2_cmplt bit for the operation-complete status.
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System Memory Controller (SMC) DEVICE ADDR SDA 3 M START S B WORD ADDR DATA A C K A W C R K A C K STOP ACK from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? N Y LOAD “$09” (START CONDITION) TO I2C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG N CMPLT=ACKIN=1? * Y LOAD “WORD ADDR” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG N CMPLT=ACKIN=1? * Y LOAD “DATA” TO I C TRANSMITTER DATA REG 2 READ I2C STATUS REG N CMPLT=ACKIN=1? * Y LOAD “$05”
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Functional Description I2C Random Read The I2C random read begins in the same manner as the I2C byte write. The first step in the programming sequence should be to test the i2_cmplt bit for the operation-complete status. The next step is to initiate a start sequence by first setting the i2_start and i2_enbl bits in the I2C Control Register and then writing the device address (bits 7-1) and write bit (bit 0=0) to the I2C Transmitter Data Register.
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System Memory Controller (SMC) DEVICE ADDR SDA 3 DEVICE ADDR WORD ADDR x A W C R K M START S B A M C START S K B R D DATA x A C K N O A C K STOP ACK and DATA from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? N Y LOAD “$09” (START CONDITION) TO I2C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG READ I2C STATUS REG CMPLT=ACKIN=1? N CMPLT=ACKIN=1? * N * Y Y LOAD “DUMMY DATA” TO TRANSMITTER DATA REG I2 C LOAD “WORD ADDR x” TO I2C TRANSMITTER DAT
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Functional Description I2C Current Address Read The I2C slave device should maintain the last address accessed during the last I2C read or write operation, incremented by one. The first step in the programming sequence should be to test the i2_cmplt bit for the operationcomplete status.
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System Memory Controller (SMC) DATA of (last ADDR+1) DEVICE ADDR SDA 3 M START S B N O A C K A R C D K STOP ACK and DATA from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? N Y LOAD “$09” (START CONDITION) TO I2C CONTROL REG LOAD “DEVICE ADDR+RD BIT” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG CMPLT=ACKIN=1? N * Y LOAD “DUMMY DATA” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG CMPLT=DATIN=1? N * Y READ I2C RECEIVER DATA REG LOAD “$05” (STOP CONDITION) TO I2C CONTROL REG LOAD “DUM
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Functional Description I2C Page Write The I2C page write is initiated the same as the I2C byte write, but instead of sending a stop sequence after the first data word, the I2C master controller will transmit more data words before a stop sequence is generated. The first step in the programming sequence should be to test the i2_cmplt bit for the operation-complete status.
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System Memory Controller (SMC) 3 SDA A C K A W C R K DATA n DATA 1 WORD ADDR 1 DEVICE ADDR M START S B A C STOP K A C K ACK from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? N Y LOAD “$09” (START CONDITION) TO I2C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG CMPLT=ACKIN=1? N * LOAD “DATA1 ...
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Functional Description I2C Sequential Read The I2C sequential read can be initiated by either an I2C random read (described here) or an I2C current address read. 3 2 The first step in the programming sequence of an I C random read initiation is to test the i2_cmplt bit for the operation-complete status.
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System Memory Controller (SMC) As long as the slave device receives an acknowledge, it will continue to increment the word address and serially clock out sequential data words. The I2C sequential read operation is terminated when the I2C master controller does not respond with an acknowledge. This can be accomplished by setting only the i2_enbl bit in the I2C Control Register before receiving the last data word.
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Functional Description DEVICE ADDR SDA DEVICE ADDR WORD ADDR 1 A W C R K M START S B A M C START S K B DATA 1 A C K A R C D K 3 DATA n N O A C K STOP ACK and DATA from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? N LOAD “DUMMY DATA” TO I2C TRANSMITTER DATA REG Y LOAD “$09” (START CONDITION) TO I2C CONTROL REG READ I2C STATUS REG LOAD “DEVICE ADDR+WR BIT” TO I2C TRANSMITTER DATA REG CMPLT=DATIN=1? N * Y READ I2C STATUS REG CMPLT=ACKIN=1? READ I2C RECEIVER DATA REG N * LOAD “$01” TO
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System Memory Controller (SMC) Refresh/Scrub The SMC performs refresh by doing a burst of 4 CAS-Before-RAS (CBR) refresh cycles to each block of SDRAM once every 60 microseconds. It performs scrubs by replacing every 128th refresh burst with a read cycle to 8 bytes in each block of SDRAM. If during the read cycle, the SMC detects a single-bit error, it performs a write cycle back to SDRAM using corrected data providing the SWEN control bit is set. It does not perform the write if the SWEN bit is cleared.
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Programming Model Chip Configuration Some configuration options in the Hawk must be configured at power-up reset time before software performs any accesses to it. The Hawk obtains this information by latching the value on some of the upper RD signals just after the rising edge of the PURST_ signal pin. The recommended way to control the RD signals during reset is to place pull-up or pull-down resistors on the RD bus.
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System Memory Controller (SMC) Register Summary Table 3-9 shows a summary of the internal and external register set.
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Programming Model Table 3-9. Register Summary (Continued) FEF80070 DPE_A FEF80078 DPE_DH FEF80080 DPE_DL 3 FEF80090 i2_enbl i2_ackout i2_stop trcd trp tdp CTR32 p0_tben FEF80100 p1_tben APE_A FEF88000 FEF8FFF8 http://www.motorola.
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System Memory Controller (SMC) Notes 1. All empty bit fields are reserved and read as zeros. 2. All status bits are shown in italics. 3. All control bits are shown with underline. 3 4. All control-and-status bits are shown with italics and underline. Detailed Register Bit Descriptions The following sections describe the registers and their bits in detail. The possible operations for each bit in the register set are as follows: R The bit is a read only status bit. R/W The bit is readable and writable.
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Programming Model Vendor/Device Register $FEF80000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address Bit Name Operation Reset VENDID DEVID READ ONLY $1057 READ ONLY $4803 VENDID This read-only register contains the value $1057. It is the vendor number assigned to Motorola Inc. DEVID This read-only register contains the value $4803. It is the device number for the Hawk.
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System Memory Controller (SMC) Software should only set the tben_en bit when there is no external L2 cache connected to the I2clm_ pin and when there is no external register set. 3 REVID The REVID bits are hard-wired to indicate the revision level of the SMC. The value for the first revision is $01. aonly_en Normally, the SMC responds to address-only cycles only if they fall within the address range of one of its enabled map decoders.
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Programming Model SDRAM Enable and Size Register (Blocks A, B, C, D) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Operation R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W Reset 0 PL X X X 0P 0P 0P 0P 0 PL X X X 0P 0P 0P 0P 0 PL X X X 0P 0P 0P 0P 0 PL X X X 0P 0P 0P 0P Name $FEF80010 ram a en 0 0 0 ram a siz0 ram a siz1 ram a siz2 ram a siz3 ram b en 0 0 0 ram b siz0 ram b siz1 ram b siz2 ram b siz3 ram
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System Memory Controller (SMC) Table 3-10.
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Programming Model SDRAM Base Address Register (Blocks A/B/C/D) Name Operation Reset $FEF80018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Bit RAM A BASE RAM B BASE RAM C BASE RAM D BASE READ/WRITE 0 PL READ/WRITE 0 PL READ/WRITE 0 PL READ/WRITE 0 PL Writes to this register must be enveloped by a period of time in which no accesses to SDRAM occur.
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System Memory Controller (SMC) CLK Frequency Register $FEF80020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLK FREQUENCY 64 P X CLK FREQUENCY READ ZERO X 1P X X X X X X X READ ZERO R/C R R R R R R R Reset READ/WRITE R/W 0-P Operation por 0 0 0 0 0 0 0 Name drr 3 Address Bit These bits should be programmed with the hexadecimal value of the operating CLOCK frequency in MHz (i.e. $42 for 66 MHz).
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Programming Model us (64 ms / 8192 rows = 7.8 us). In order for Hawk 1 or 2 to accommodate such SDRAM’s their CLK_FREQUENCY must be programmed with the CLK pin (bus clock) frequency divided by two. For example, if the clock pin frequency is 100 MHz, the CLK_FREQUENCY register should be programmed with $32 (100 MHz divided by 2) rather than $64. The same work-around can, but does not have to be used for Hawk 3.
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System Memory Controller (SMC) ECC Control Register 0PL 0PL 0 PL 0 PL 0 PL 0PL X X X 1 PL 0 PL 0 PL X X X X X 3-46 0 PL X X X X X X X R/C R/W R/W R/W R/W R/W R R R R/W R/W R/W R R R R R Reset READ ZERO R/W R R R R R R R Operation mbe_me 0 0 0 0 0 0 0 int mien sien dpien scien apien 0 0 0 derc rwcb refdis 0 0 0 0 0 Name $FEF80028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 Address Bit refdis When set, refdis causes the refresher and all of its asso
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Programming Model 0 3 Normal View of Data (rwcb=0) 64 bits 0 1 2 3 4 5 6 7 Check-bit View (rwcb=1) Figure 3-10. Read/Write Check-bit Data Paths Note that if test software attempts to force a single-bit error to a location using the rwcb function, the scrubber may correct the location before the test software gets a chance to check for the single-bit error. This can be avoided by disabling scrub writes. Also note that writing bad check-bits can set the elog bit in the Error Logger Register.
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System Memory Controller (SMC) 5. Clear the derc and rwcb bits in the Data Control register. 6. Perform the desired testing related to the location/locations that have had their check-bits altered. 3 7. Enable scrub writes by setting the swen bit if it was set before. derc Setting derc to one alters SMC operation as follows: 1. During reads, data is presented to the PPC60x data bus uncorrected from the SDRAM array. 2.
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Programming Model sien When sien is set, the logging of a single-bit error causes the int bit to be set if it is not already. When the int bit is set, the Hawk’s internal error interrupt is asserted. mien When mien is set, the logging of a non-correctable error causes the int bit to be set if it is not already. When the int bit is set, the Hawk’s internal error interrupt is asserted. int int is set when one of the SMC’s interrupt conditions occurs.
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System Memory Controller (SMC) Error Logger Register Address READ ONLY R/C R R R R R R R READ/WRITE 0P 0P X X X 0P 0P 0P X 3-50 scof 0 0 0 esblk2 esblk1 esblk0 0 Reset SBE_COUNT 0P 0P 0 PL 0P X X X 0P Operation ERR_SYNDROME R R R/W R R R R R/C Name esbt embt esen escb 0 0 0 elog 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $FEF80030 Bit 0P elog When set, elog indicates that a single- or a multiple-bit error has been logged by the SMC.
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Programming Model esbt esbt is set by the logging of a single-bit error. It is cleared by the logging of a multiple-bit error. When the SMC logs a single-bit error, the syndrome code indicates which bit was in error. Refer to the section on SDRAM ECC Codes. ERR_SYNDROME ERR_SYNDROME reflects the syndrome value at the last logging of an error. This eight-bit code indicates the position of the data error. When all the bits are zero, there was no error.
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System Memory Controller (SMC) Error_Address Register Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit Name X R 0 X R 0 X R 0 ERROR_ADDRESS Operation READ ONLY 0P Reset ERROR_ADDRESS These bits reflect the value that corresponds to bits 0-28 of the PPC60x address bus when the SMC last logged an error during a PowerPC access to SDRAM. They reflect the value of the SCRUB ADDRESS counter if the error was logged during a scrub cycle.
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Programming Model Note that when this register is all 0’s, the scrub prescale counter does not increment, disabling any scrubs from occurring. Since SCRUB_FREQUENCY is cleared to 0’s at power-up reset, scrubbing is disabled until software programs a non-zero value into it.
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System Memory Controller (SMC) ROM A Base/Size Register $FEF80050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0 PL 0 PL VP X X X X X $FF0 PL Reset READ ZERO R/W R/W R/W R R R R R READ/WRITE rom a we rom a en rom_a_rv 0 0 0 0 0 Operation 0 PL 0 PL 0 PL VP ROM A BASE R/W R/W R/W R Name rom a siz2 rom a siz1 rom a siz0 rom_a_64 3 Address Bit Writes to this register must be enveloped by a period of time in which no accesses to ROM/Flash Block A, occur
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Programming Model each half of the SMC interfaces to 32 bits. rom_a_64 matches the value that was on the RD2 pin at power-up reset. It cannot be changed by software. rom a siz The rom a siz control bits are the size of ROM/Flash for Block A. They are encoded as shown in Table 3-11. Table 3-11.
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System Memory Controller (SMC) rom_a_rv is initialized at power-up reset to match the value on the RD0 pin. rom a en 3 When rom a en is set, accesses to Block A ROM/Flash in the address range selected by ROM A BASE are enabled. When rom a en is cleared, they are disabled. rom a we When rom a we is set, writes to Block A ROM/Flash are enabled. When rom a we is cleared, they are disabled. Note that if rom_a_64 is cleared, only 1-byte writes are allowed. If rom_a_64 is set, only 4-byte writes are allowed.
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Programming Model ROM B Base/Size Register 31 30 29 28 27 26 R/W R/W R/W R R R R X 0 PL 0 PL VP X X X X X R 0 PL 0 PL 0 PL VP rom b we rom b en rom_b_rv 0 0 0 0 0 $FF4 PL 25 R/W R/W R/W R READ ZERO 24 rom b siz2 rom b siz1 rom b siz0 rom_b_64 READ/WRITE 23 ROM B BASE 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Reset 1 Operation $FEF80058 0 Address Bit Name Writes to this register must be enveloped by a period of time in which no accesses to ROM/Fl
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System Memory Controller (SMC) rom_b_64 rom_b_64 indicates the width of ROM/Flash device/devices being used for Block B. When rom_b_64 is cleared, Block B is 16 bits wide, where each half of the SMC interfaces to 8 bits. When rom_b_64 is set, Block B is 64 bits wide, where each half of the SMC interfaces to 32 bits. rom_b_64 matches the value that was on the RD3 pin at power-up reset. It cannot be changed by software. 3 rom b siz The rom b siz control bits are the size of ROM/Flash for Block B.
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Programming Model rom b we When rom b we is set, writes to Block B ROM/Flash are enabled. When rom b we is cleared, they are disabled. Refer back to Table 3-13 for more details.
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System Memory Controller (SMC) Writes that change these bits must be enveloped by a period of time in which no accesses to ROM/Flash Block A, occur. A simple way to provide the envelope is to perform at least two accesses to this or another of the SMC’s registers before and after the write. 3 Table 3-15. ROM Speed Bit Encodings rom_a/b_spd0,1 Approximate ROM Block A/B Device Access Time %00 12 Clock Periods (120ns @ 100 MHz, 180ns @ 66.67 MHz) %01 8 Clock Periods (80ns @ 100 MHz, 120ns @ 66.
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Programming Model Data Parity Error Log Register Address 0 1 X 2 0P 3 0P 4 0P 5 0P 6 0P 7 8 9 10 11 12 13 14 15 16 X R 0 17 X R 0 18 X R 0 19 X R 0 20 X R 0 21 X R 0 0 PL R/W dpe_ckall 22 0 PL R/W dpe_me 23 24 25 26 27 28 29 30 31 Reset dpelog 0 0 dpe_tt0 dpe_tt1 dpe_tt2 dpe_tt3 dpe_tt4 Operation DPE_DP GWDP R/C R R R R R R R Name $FEF80068 READ ONLY READ/WRITE 0P 0 PL 0P Bit dpelog dpelog is set when a parity error occurs on the PPC60x data bus during a PPC60x data cycle whose parity the S
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System Memory Controller (SMC) Data Parity Error Address Register Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit Name DPE_A Operation READ ONLY 0 PL Reset DPE_A DPE_A is the address of the last PPC60x data bus parity error that was logged by the Hawk. It is updated only when dpelog goes from 0 to 1.
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Programming Model Data Parity Error Lower Data Register Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit $FEF80080 Name DPE_DL Operation READ ONLY 0 PL Reset DPE_DL DPE_DL is the value on the lower half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk. It is updated only when dpelog goes from 0 to 1. http://www.motorola.
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System Memory Controller (SMC) I2C Clock Prescaler Register Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 $FEF80090 Name Operation I2_PRESCALE_VAL READ ZERO READ ZERO READ/WRITE X X $01F3 P Reset I2_PRESCALE_VAL I2_PRESCALE_VAL is a 16-bit register value that will be used in the following formula for calculating frequency of the I2C gated clock signal: I2C CLOCK = SYSTEM CLOCK/ (I2_PRESCALE_VAL +1)/2 After power-up, I2_PRESCALE_VAL is initialized
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Programming Model When set, the I2C master controller generates a stop sequence on the I2C bus on the next dummy write (data=don’t care) to the I2C Transmitter Data Register and clears the i2_cmplt bit in the I2C Status Register. After the stop sequence has been transmitted, the I2C master controller will automatically clear the i2_stop bit and then set the i2_cmplt bit in the I2C Status Register.
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System Memory Controller (SMC) Register, and further writes to the I2C Control Register will not be allowed until after the I2C Status Register is read. A read from the I2C Status Register will clear this bit. 3 i2_ackin This bit is set if the addressed slave device is acknowledged to either a start sequence or data writes from the I2C master controller and cleared otherwise. The I2C master controller will automatically clear this bit at the beginning of the next valid I2C operation.
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Programming Model I2C Receiver Data Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 $FEF800B0 0 Address Bit Name Operation Reset I2_DATARD READ ZERO READ ZERO READ ZERO READ X X X 0 PL The I2_DATARD contains the receive byte for I2C data transfers. During I2C sequential read operation, the current receive byte must be read before any new one can be brough in.
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System Memory Controller (SMC) ram e/f/g/h en ram e/f/g/h en enables accesses to the corresponding block of SDRAM when set, and disables them when cleared. Note that ram a/b/c/d en are located at $FEF80010 (refer to the section on SDRAM Enable and Size Register (Blocks A,B,C,D) in a previous section). They operate the same for blocks A-D as these bits do for blocks E-H. 3 ram e/f/g/h siz0-3 These control bits define the size of their corresponding block of SDRAM.
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Programming Model Note that RAM A/B/C/D BASE are located at $FEF80018 (refer to the section titled SDRAM Base Address Register (Blocks A/B/C/D) for more information). They operate the same for blocks A-D as these bits do for blocks E-H. Also note that the combination of RAM_X_BASE and ram_x_siz should never be programmed such that SDRAM responds at the same address as the CSR, ROM/Flash, External Register Set, or any other slave on the PowerPC bus.
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System Memory Controller (SMC) cl3 When cl3 is cleared, the SMC assumes that the SDRAM runs with a CAS_ latency of 2. When cl3 is set, the SMC assumes that it runs with a CAS_ latency of 3. Note that writing so as to change cl3 from 1 to 0 or vice-versa causes the SMC to perform a mode-register-set operation to the SDRAM array. The moderegister-set operation updates the SDRAM’s CAS latency to match cl3.
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Programming Model swr_dpl swr_dpl causes the SMC to always wait until four clocks after the write command portion of a single write before allowing a precharge to occur. This function may not be required. If such is the case, swr_dpl can be cleared by software. tdp tdp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Tdp parameter. When tdp is 0, the minimum time provided for Tdp is 1 clock. When tdp is 1, the minimum is 2 clocks.
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System Memory Controller (SMC) 3 ape_ap0-3 APE_AP is the value that was on the AP0-AP3 signals when the apelog bit was set. ape_me When ape_me is set, the transition of the apelog bit from false to true causes the Hawk to pulse its machine check interrupt request pin (MCHK0_) true. When ape_me is cleared, apelog does not affect the MCHK0_ pin.
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Programming Model 32-Bit Counter Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit $FEF80100 Name CTR32 Operation READ/WRITE Reset 0 PL CTR32 Note CTR32 is a 32-bit, free-running counter that increments once per microsecond if the CLK_FREQUENCY register has been programmed properly. Notice that CTR32 is cleared by power-up and local reset. When the system clock is a fractional frequency, such as 66.
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System Memory Controller (SMC) The Hawk’s EXTERNAL REGISTER SET interface is similar to that for ROM/Flash Block A and B. In fact, another name for the External Register Set is ROM/Flash Block C. The differences between Blocks A/B and C are that the following parameters are fixed rather than programmable for Block C. 3 1. The device speed for Block C is fixed at 11 Clocks. 2. The width for Block C is fixed at 64 bits. 3.
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Software Considerations When the tben_en bit is cleared, p1_tben has no effect on any pin. p0_tben When the tben_en bit is set, the ERCS_ output pin becomes the P1_TBEN output pin and it tracks the value on p0_tben. When p0_tben is 0, the P0_TBEN pin is low and when p1_tben is 1, the P0_TBEN pin is high. When the tben_en bit is cleared, p0_tben has no effect on any pin.
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System Memory Controller (SMC) Some registers have additional requirements for writing. For more information refer to the register sections in this chapter titled SDRAM Enable and Size Register (Blocks A,B,C,D), SDRAM Base Address Register (Blocks A/B/C/D), SDRAM Enable and Size Register (Blocks E,F,G,H), SDRAM Base Address Register (Blocks E/F/G/H), and SDRAM Speed Attributes Register.
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Software Considerations SDRAM Size The SDRAM size control bits come up from power-up reset cleared to zero. Once software has determined the correct size for an SDRAM block, it should set the block’s size bits to match. The value programmed into the size bits tells the Hawk how big the block is (for map decoding), and how to translate that block’s 60x addresses to SDRAM addresses. Programming a block’s size to non-zero also allows it to participate in scrubbing if scrubbing is enabled.
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System Memory Controller (SMC) SDRAM Control Registers Initialization Example The following is a possible sequence for initializing SDRAM control registers: 3 1. Get a small piece of SDRAM for software to use for this routine (optional). This routine assumes that SDRAM related control bits are still at the power-up-reset default settings. We will use a small enough piece of SDRAM that the address signals that are affected by SDRAM size will not matter. For each SDRAM block: a.
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Software Considerations c. If a CAS latency of 2 is supported, check SPD byte 23 to determine the CAS_latency _2 cycle time. If the CAS_latency_2 cycle time is less than or equal to the period of the system clock then this block can operate with a CAS latency of 2. Otherwise a CAS latency of 3 is all that is supported for this block. If any block does not support a CAS latency of 2, then cl3 is to be set. If all of the blocks support a CAS latency of 2, then the cl3 bit is to be cleared.
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System Memory Controller (SMC) Table 3-18.
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Software Considerations Notes 1. Use tRAS from the SDRAM block that has the slowest tRAS. 2. tRAS_CLK is tRAS expressed in CLK periods. 3. Use tRP from the SDRAM block that has the slowest tRP. 4. tRP_CLK is tRP expressed in CLK periods. 5. Use tRCD from the SDRAM block that has the slowest tRCD. 6. tRCD_CLK is tRCD expressed in CLK periods. 7. Use tRC from the SDRAM block that has the slowest tRC. 8. tRC_CLK is tRC expressed in CLK periods. 9. Remember that CLK is the Hawk’s 60x clock input pin. 5.
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System Memory Controller (SMC) Table 3-19. Programming SDRAM SIZ Bits 3 Total Number of Locations within the Block (L) 1 Primary Device Width 2 Block Size 3 Value to be programmed into the Block’s ram_x_siz bits 4 4M 16 32MB %0001 8M 8 64MB %0010 8M 16 64MB %0011 16M 4 128MB %0100 16M 8 128MB %0101 16M 16 128MB %0110 32M 4 256MB %0111 32M 8 256MB %1000 64M 4 512MB %1001 Notes 1.
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Software Considerations 8. Now that at least one refresh has occurred since SDRAM was last accessed, it is okay to write to the SDRAM control registers. a. Program the SDRAM Speed Attributes Register using the information obtained in steps 3 and 4 and the fact that the swr_dp and tdp bits should be set to 1’s. 3 b. Program the SDRAM Base Address Register (Blocks A/B/C/D) and the SDRAM Base Address Register (Blocks E/F/G/H).
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System Memory Controller (SMC) Optional Method for Sizing SDRAM Generally SDRAM block sizes can be determined by using SPD information (refer to the previous section on SDRAM Control Registers Initialization example). Another method for accomplishing this is as follows: 3 1. Initialize the SMC’s control register bits to a known state. a. Clear the isa_hole bit (refer to the section titled Vendor/Device Register for more information.) b.
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Software Considerations 2. For each of the Blocks A through H: a. Set the block’s base address to $00000000. Refer to the sections titled SDRAM Base Address Register (Blocks A/B/C/D) and SDRAM Enable and Size Register (Blocks E,F,G,H). b. Enable the block and make sure that the other seven blocks are disabled. Refer to the same sections as referenced in the previous step. c. Set the block’s size control bits. Start with the largest possible (512MB).
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System Memory Controller (SMC) Table 3-20. Address Lists for Different Block Size Checks 3 512MB (64Mx4) 256MB (32Mx8) 256MB (32Mx4) 128MB (16Mx16) 128MB (16Mx8)1 128MB (16Mx4)1 $00000000 $00008000 $10000000 $00000000 $00004000 $08000000 $00000000 $00008000 $00000000 $04000000 $00000000 $00004000 $00000000 $00004000 64MB (8Mx16)2 64MB (8Mx8)2 32MB (4Mx16)3 $00000000 $00002000 $00000000 $00002000 $00000000 $00001000 Notes 1. 16Mx8 and 16Mx4 are the same.
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ECC Codes ECC Codes When the Hawk reports a single-bit error, software can use the syndrome that was logged by the Hawk to determine which bit was in error. Table 3-21 shows the syndrome for each possible single bit error. Table 3-22 shows the same information ordered by syndrome. Table 3-21.
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System Memory Controller (SMC) Table 3-22.
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4Hawk Programming Details 4 Introduction This chapter contains details of several programming functions associated with the Hawk ASIC chip. PCI Arbitration PCI arbitration must be provided by the host board. Hawk MPIC External Interrupts The MVME5100 Hawk MPIC is fully compliant with the industry standard Multi-Processor Interrupt Controller Specification. Following a power-up reset, the MPIC is configured to operate in the parallel interrupt delivery mode on the MVME5100 series: Table 4-1.
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Hawk Programming Details Table 4-1. MPIC Interrupt Assignments (Continued) 4 MPIC IRQ Edge/ Level Polarity Interrupt Source IRQ9 Level Low PCI-PMC1 INTA#, PMC2 INTB#, PCIX INTA# IRQ10 Level Low PCI-PMC1 INTB#, PMC2 INTC#, PCIX INTB# IRQ11 Level Low PCI-PMC1 INTC#, PMC2 INTD#, PCIX INTC# IRQ12 Level Low PCI-PMC1 INTD#, PMC2 INTA#, PCIX INTD# IRQ13 Level Low PCI-Ethernet Device Port 2 (Front panel or P2) IRQ14 Level Low ABORT_L IRQ15 Level Low RTC - Alarm Notes 1 Notes 1.
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PCI Arbitration 8259 Interrupts There are 15 interrupt requests supported by the Peripheral Bus Controller (PBC), which is only available if an IPMC761 or IPMC712 is installed. These 15 interrupts are ISA-type interrupts that are functionally equivalent to two 82C59 interrupt controllers. Except for IRQ0, IRQ1, IRQ2, IRQ8_, and IRQ13, each of the interrupt lines can be configured for either edge-sensitive mode or level-sensitive mode by programming the appropriate ELCR registers in the PBC.
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Hawk Programming Details Table 4-2.
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Exceptions Exceptions Sources of Reset There are five potential reset sources on the MVME5100 series. They are as follows: 1. Power-On Reset 2. RESET Switch 3. Watchdog Timer Reset 4. Software generated Module Reset using MODRST Bit Register. 5. Reset generated from system bus Each source of reset will result in a reset of the processor, Hawk ASIC, and all other on-board logic. The PMC RESETOUT_L pin will also be activated by all reset sources except for the PMC PCI RST# input.
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Hawk Programming Details Error Notification and Handling The Hawk ASIC can detect certain hardware errors and can be programmed to report these errors via the MPIC interrupts or the Machine Check Interrupt. The following table summarizes how the hardware errors are handled by the MVME5100 series: 4 Table 4-3.
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Endian Issues Endian Issues The MVME5100 series supports both Little and Big-Endian software. Because the PowerPC processor is inherently big endian, and PCI is inherently Little-Endian, it is easy to misinterpret the processing scheme. For that reason, provisions have been made to accommodate the handling of endian issues within the MVME5100.
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Hawk Programming Details Little-Endian PROGRAM Little Endian Big Endian EA Modification (XOR) 4 Hawk DRAM 60X System Bus Hawk Big-Endian EA Modification Little-Endian PCI Local Bus Figure 4-2.
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Endian Issues Processor/Memory Domain The MPC750 processor can operate in both Big-Endian and Little-Endian modes. However, it always treats the external processor/memory bus as Big-Endian by performing address rearrangement and reordering when running in Little-Endian mode. The MPIC registers inside the Hawk, the registers inside the SMC, the SDRAM, the ROM/FLASH, and the system registers always appear as Big-Endian.
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ARelated Documentation A Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: ❏ Contacting your local Motorola sales office ❏ Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature Table A-1.
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A Manufacturers’ Documents Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As an additional help, a source for the listed document is provided. Please note that while these sources have been verified, the information is subject to change without notice. Table A-2.
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Related Documentation Table A-2. Manufacturers’ Documents (Continued) Document Title Publication Number Texas Instruments TL16C550C UART Data Sheet Texas Instruments http://www.ti.com TL16550 M48T37V CMOS 32Kx8 Timekeeper SRAM Data Sheet SGS Thomson Microelectronics tap//.us.st.com M48T37V 2-Wire Serial CMOS EEPROM Data Sheet Atmel Corporation http://www.atmel.com/atmel/support/ AT24C04 http://www.motorola.
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A Related Specifications Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice. Table A-3. Related Specifications Publication Number Document Title and Source Peripheral Component Interconnect (PCI) Interface Specification, Revision 2.1 PCI Special Interest Group P.O.
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BMVME5100 VPD Reference Information B Vital Product Data (VPD) Introduction Vital Product Data (VPD) consists of data items that are pertinent to board configuration and operation. This appendix includes information on how to perform various tasks to read, modify and correct Vital Product Data, as well as general format and content information for this product.
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MVME5100 VPD Reference Information – Displays most of the identification strings and hardware clock frequencies B ❏ Serial EEPROM command - srom;i – Can be used as a byte viewer ❏ Indirect block move command - ibm;i – Reads the entire SROM block to memory ❏ Memory display command - md – Can be used to display a VPD block which has been copied to memory ❏ Network I/O physical command - niop – Can be used to upload a VPD block from memory to a network file How to Modify the VPD Informati
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Vital Product Data (VPD) Introduction What Happens if the VPD Information is Corrupted? B If for some reason, the VPD information becomes corrupted, the following occurs: ❏ A warning is displayed in the startup banner ❏ The firmware ignores the VPD contents and attempts to acquire information from other sources ❏ Some device drivers will not work ❏ Some diagnostic tests fail ❏ The board runs much slower than usual How to Fix Corrupted VPD Information ❏ The firmware is designed to reach the pro
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MVME5100 VPD Reference Information B ❏ Press the abort switch during startup (double-button reset reset/abort) to enter the safe mode (at this point, the firmware will ignore all SROM contents and reset) ❏ Use the srom, ibm, or update command to change the VPD to the correct parameters The data listed in the following tables are for general reference information.
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Vital Product Data (VPD) Introduction Table B-1. VPD Packet Types (Continued) ID# Size Description B Data Type Notes 06 04 MPU External Clock Frequency in Hertz (e.g., 100,000,000 decimal, etc.). This is also called the local processor bus frequency. Integer (4byte) 2 07 04 Reference Clock Frequency in Hertz (e.g., 32,768 decimal, etc.). This value is the frequency of the crystal driving the OSCM. Integer (4byte) 2 08 06 Ethernet Address (e.g., 08003E26A475, etc.
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MVME5100 VPD Reference Information Table B-1. VPD Packet Types (Continued) B ID# 0F Size 04 Description Data Type VPD Revision. A table found later in this section further describes this packet. 10BF Reserved C0FE User Defined An example of a user defined packet could be the type of LCD panel connected in an MPC821 based application. FF N/A Termination Packet (follows the last initialized data packet) Notes Binary N/A Notes: 1. Data size varies, depending on the product configuration/type.
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Vital Product Data (VPD) Introduction VPD Definitions - Product Configuration Options Data B The product configuration options data packet consists of a binary bit field. The first bit of the first byte is bit 0 (i.e., PowerPC bit numbering). An option is present when the assigned bit is a one. the following table further describes the product configuration options VPD data packet: Table B-2.
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MVME5100 VPD Reference Information Table B-2.
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Vital Product Data (VPD) Introduction VPD Definitions - FLASH Memory Configuration Data B The FLASH memory configuration data packet consists of byte fields which indicate the size/organization/type of the FLASH memory array. The following table(s) further describe the FLASH memory configuration VPD data packet. Table B-3.
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MVME5100 VPD Reference Information B VPD Definitions - L2 Cache Configuration Data The L2 cache configuration data packet consists of byte fields that show the size, organization, and type of the L2 cache memory array. Note: The PPMCBASE does not contain L2 Cache . The following table(s) further describe the L2 cache memory configuration VPD data packet. Table B-4.
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Vital Product Data (VPD) Introduction Table B-4.
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MVME5100 VPD Reference Information B VPD Definitions - VPD Revision Data The VPD revision data packet consists of byte fields that indicate the type, version, and revision of the vital product data. The following table(s) further describe the VPD revision data packet. Table B-5.
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Vital Product Data (VPD) Introduction SROM_CRC.C B /* * srom_crc - generate CRC data for the passed buffer * description: * This function’s purpose is to generate the CRC for the * passed buffer.
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MVME5100 VPD Reference Information B Configuration Checksum Calculation Code /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * cssect - checksum section * description: * This component's purpose is to checksum the buffer pointed to * by the buffer pointer.
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Vital Product Data (VPD) Introduction Serial Presence Detect (SPD) Checksum Calculation B The checksum field (Byte 63) designates the checksum for checking data integrity (similar to parity) for bytes 0-62. It is written during board production and can be used to verify the data integrity for these bytes. The process for calculating the Checksum includes the following: 1. Convert the binary information in byte locations 0-62 to decimal. 2. Add together (sum) all decimal values for addresses 0-62. 3.
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MVME5100 VPD Reference Information Example of a Checksum Calculation: B SPD Byte Address Serial PD 00 (0x00) 0010 0100 > 36 01 (0x01) 1111 1110 > +254 02 (0x02) 0000 0000 > +0 03 (0x03) 0000 0000 > +0 : : : : > +0 60 (0x3C) 0000 0000 > +0 61 (0x3D) 0000 0000 > +0 62 (0x3E) 0000 0000 > +0 SPD Byte Address Serial PD Decimal Total - - 290 Divide by 256 - - 1 Remainder - - 34 Convert to binary 0010 0010 < 34 63(0x3F)(Checksum) 0010 0010 - B-16 Convert t
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CVMEbus Mapping Example C Introduction This appendix contains an application note on establishing addressability on the VMEbus using the MVME5100 and MVME2700 boards as examples. Future Motorola board level documents may contain additional application notes aimed at clarifying configuration or implementation issues that have been noted by several Motorola customers. If you are unsure if this application will work on your particular product configuration, contact your Motorola sales representative.
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C Introduction The MVME2700 board, which uses a PReP memory map, is configured in this example to occupy address space from 1000 0000 to 13FF FFFF (64MB) on the VMEbus. The MVME5100, which defaults to a CHRP memory map, occupies another 64MB address range, which in this example is from 1400 0000 to 17FF FFFF. The PCI Slave Images represent the view of the Universe on the PCI Local Bus. The VME Slave Images represent the view of the Universe on the VMEbus.
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VMEbus Mapping Example 0000 on the PCI Local bus. Thus, to translate an inbound address of 1000 0000 (the configured VMEbus Base address of this board to 8000 0000, which is presented to DRAM as 0000 0000 and translation value of 7000 0000 is selected: 1000 0000 + 7000 0000 => 8000 0000 on the PCI Local Bus that becomes 0000 0000 on the PowerPC bus. 5100 PCI Slave Translate In the CHRP memory map, PCI Memory Space is based at 8000 0000.
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Index Numerics 32-Bit Counter 3-73 SMC 3-73 8259 Interrupts 4-3 A A0-A31 3-4 AACK as used with PPC Slave 2-7 access timing (ROM) 3-19, 3-20 address Address Parity Error Address Register 3-72 Address Parity Error Log Register SMC 3-71 data stepping 2-29 decoders PCI to PPC 2-6 decoders PPC to PCI 2-7 limits on PHB map decoding 2-6 mapping PPC 2-6 modification for little endian transfers 2-40 offsets, as part of map decoders 2-21 parity PPC60x 3-10 pipelining 3-6 transfers 3-9 addressing mode for PCI Master
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Index C I N D E X cache coherency restrictions 3-11 coherency SMC 3-11 support 2-25, 2-29 Cache Control Register 1-10 Cache Speed 1-10 CHRP memory 1-4 CHRP Memory Maps (suggested) 1-6 CLK FREQUENCY 3-44 CLK Frequency Register SMC 3-44 clock frequency 3-44 combining, merging, and collapsing 2-28 command types 2-23 from PCI Master 2-27 PPC slave 2-8 CONADD and CONDAT Registers 1-19 CONFIG_ADDRESS Register 2-106 CONFIG_DATA Register 2-109 configuration options on Hawk 3-35 registers 2-19 requirements on Haw
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E ECC Codes Hawk 3-87 SMC 3-11 ECC Control Register SMC 3-46 ECC memory 1-11 EEPROM 1-1 EEPROM access 3-77 elog 3-50 embt 3-50 endian conversion 2-38 endian issues MVME5100 4-7 End-of-Interrupt Registers 2-128 Error Address Register SMC 3-52 error correction 3-11 Error Correction Codes Hawk 3-87 error detection 3-11 error handling 2-41 Error Logger Register 3-50 SMC 3-50 error logging 3-13 SMC 3-13 error notification and handling 4-6 Hawk 4-6 error reporting 3-12 ERROR_ADDRESS 3-52 ERROR_SYNDROME 3-51 esbt
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Index Global Configuration Register 2-114 H I N D E X Hardware Control-Status Register 2-77 Hawk address parity 3-10 as MPU/PCI bus bridge controller ASIC 1-15 block diagram 2-3 configuration options 3-35 data parity 3-10 ECC Codes 3-87 Error Correction Codes 3-87 error notification and handling 4-6 I2C Byte Write 3-23 I2C Current Address Read 3-27 I2C Page Write 3-29 I2C Random Read 3-25 I2C Sequential Read 3-31 MPIC control registers 2-22 MPIC interrupt assignments 4-1 MPIC interrupts 4-1 MPIC registe
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L L2 Cache 1-1, 1-9 L2 Cache SRAM Size 1-10 L2 cache support SMC 3-11 L2CLK bits 1-10 L2CLM_ 3-11 latency PCI Slave 2-25 Little Endian mode of PPC devices 2-39 little-endian mode 4-8 Lock Resolution programmable 2-46 M Main Memory 1-2 map decoders PPC to PCI 2-7 mapping PPC address 2-6 master initiated termination 2-28 mcken 3-49 memory ECC 1-11 Memory Base Register 2-102 Memory Controller 1-2 memory map CHRP 1-5 PCI local bus 1-4, 1-8 processor (default) 1-4 Memory maps 1-4 memory maps 1-4 VMEbus 1-8 Memo
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Index I N D E X functions of Master 2-26 Interface features 2-1 Master Command Codes 2-27 Master explained 2-4 purpose of interface 2-19 registers 2-97 slave 2-22 Slave disconnect scenarios 2-24 slave response command types 2-23 Slave with PCI Master 2-26 speculative requests 2-47 spread I/O address translation 2-31 to MPC address decoding 2-20 to MPC address translation 2-21 write posting 2-26 PCI / VME Memory Map 1-7 PCI Arbitration Assignments for Hawk ASI 1-15 PCI bus 1-8 PCI Command/ Status Registers
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devices, when Big-Endian 2-38 Master 2-10 Master, Bug Hog 2-14 Master, doing prefetched reads 2-13 Master, read ahead mode 2-12 parity 2-17 register map 2-68 registers 2-68 slave’s role 2-7 to PCI address translation 2-7 write posting 2-9 PPC Arbiter debug functions 2-16 parking modes 2-16 prioritization schemes 2-16 PPC Arbiter Control Register 2-73 PPC Error Address Register 2-84 PPC Error Attribute Register - EATTR 2-85 PPC Error Enable Register 2-79 PPC Error Status Register 2-82 PPC Slave Address (0,1
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Index Header Type 2-101 Interprocessor Interrupt Dispatch 2-126 Interrupt Acknowledge 2-127 IPI Vector/Priority (MPIC) 2-117 MPIC 2-110 MPIC I/O Base Address 2-102 MPIC Memory Base 2-102 PCI 2-97 PCI Interrupt Acknowledge 2-87 PCI Slave Address 2-103 PCI Slave Attribute 2-104 PHB-Detected Errors Destination 2-126 PHB-Detected Errors Vector/Priority 2-125 PPC Error Address 2-84 PPC Error Attribute 2-85 PPC Error Enable 2-79 PPC Error Status 2-82 PPC Slave Address 2-90 PPC Slave Offset/Attribute 2-89, 2-91 P
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rom_a_rv and rom_b_rv encoding 3-55 rom_a_siz 3-55 rom_a_we 3-56 rom_b_64 3-58 ROM_B_BASE 3-57 rom_b_en 3-58 rom_b_rv 3-58 rom_b_siz 3-58 rom_b_we 3-59 Row Address 3-53 rwcb 3-46 S SBC mode 1-11 SBE_COUNT 3-51 scb0,scb1 3-52 scien 3-48 scof 3-51 scrub counter 3-52 Scrub Write Enable control bit 3-52 Scrub/Refresh Register SMC 3-52 SDRAM block organization 3-9 connections (block diagram) 3-4 Operational Method for Sizing 3-84 registers initializing 3-76 sizing 3-77 speed attributes 3-76 speeds 3-7 SDRAM Att
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Index I N D E X SDRAM Enable and Size Register 3-41, 3-67 SDRAM Speed Attributes Register 3-69 Vendor/Device Register 3-39 SMC Data Parity Error Address Register 3-62 SMC Data Parity Error Log Register 3-61 SMC Data Parity Error Lower Data Register 3-63 SMC External Register Set 3-73 SMC Scrub Address Register 3-53 SMC tben Register 3-74 soft reset MPIC 4-5 software considerations 3-75 Hawk 3-75 Software Readable Header Register 1-29 sources of reset MVME5100 4-5 SPD 3-77 SPD JEDEC standard definition 1-1
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VME Processor Module MVME510x 1-1 VMEbus 1-2 memory map 1-8 memory maps 1-8 VPD B-1 VPD - FLASH Memory Configuration Data B-9 VPD - L2 Cache Configuration Data B-10 VPD - Product Configuration Options B-7 VPD - Revision Data B-12 VPD definitions B-4 VPD SROM 1-10 VPD/SPD explained 1-14 W Watchdog Timer registers 2-43 watchdog timers as part of PHB 2-42 WDTxCNTL register 2-43 WDTxCNTL Registers 2-92 WDTxSTAT Registers 2-96 write posting as part of PHB tuning 2-11 writing to the control registers 3-75 Z Z85
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