Laptop User Manual

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System Memory Controller (SMC)
3
Figure 3-8. Programming Sequence for I
2
C Page Write
READ I
2
C STATUS REG
CMPLT=1? N
Y
LOAD “WORD ADDR 1” TO
I
2
C TRANSMITTER DATA REG
LOAD “DATA1 ... DATA n” TO
I
2
C TRANSMITTER DATA REG
READ I
2
C STATUS REG
CMPLT=ACKIN=1?
N
Y
READ I
2
C STATUS REG
CMPLT=ACKIN=1?
N
Y
LOAD “$09” (START CONDITION) TO
I
2
C CONTROL REG
LOAD “DEVICE ADDR+WR BIT” TO
I
2
C TRANSMITTER DATA REG
READ I
2
C STATUS REG
CMPLT=ACKIN=1?
N
Y
LOAD “$05” (STOP CONDITION) TO
I
2
C CONTROL REG
LOAD “DUMMY DATA” TO
I
2
C TRANSMITTER DATA REG
READ I
2
C STATUS REG
CMPLT=1?
N
Y
START
STOP
SDA
S
B
M
DEVICE ADDR
W
R
A
C
K
WORD ADDR 1
A
C
K
DATA 1
A
C
K
ACK from Slave Dev
ice
END
BEGIN
*
*
*
(*) : Stop condition should be generated to abort the transfer after a software wait loop (~1ms) has been expired
DATA n
A
C
K
LAST BYTE ?
N
Y