MVME5100 Single Board Computer Installation and Use V5100A/IH4 July 2003 Edition
© Copyright 2003 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola and the Motorola logo are registered trademarks and AltiVec is a trademark of Motorola, Inc. PowerPC and the PowerPC logo are registered trademarks; and PowerPC 750 is a trademark of International Business Machines Corporation and are used by Motorola, Inc. under license from International Business Machines Corporation.
Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware.
Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution ! Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection. Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry.
CE Notice (European Community) Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC).
Limited and Restricted Rights Legend If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.
Contents About This Manual Summary of Changes ................................................................................................xvii Overview of Contents ...............................................................................................xvii Comments and Suggestions .......................................................................................xix Conventions Used in This Manual.............................................................................xix Terminology.....
DEBUG Port ............................................................................................... 2-3 System Powerup ........................................................................................................ 2-3 Initialization Process .......................................................................................... 2-4 CHAPTER 3 PPCBug Firmware Introduction ...............................................................................................................
CHAPTER 5 Pin Assignments Introduction................................................................................................................5-1 Summary.............................................................................................................5-1 Jumper Settings ..........................................................................................................5-2 Connectors ...................................................................................................
EMC Compliance ..................................................................................................... A-3 APPENDIX B Troubleshooting Solving Startup Problems ......................................................................................... B-1 APPENDIX C Related Documentation Motorola Computer Group Documents .................................................................... C-1 Manufacturers’ Documents ............................................................................
List of Figures Figure 1-1. MVME5100 Layout ................................................................................1-9 Figure 1-2. MVME5100 Installation and Removal From a VMEbus Chassis ........1-11 Figure 1-3. Typical PMC Module Placement on an MVME5100 ...........................1-11 Figure 1-4. PMCspan-002 Installation on an MVME510 .......................................1-13 Figure 1-5. PMCspan-010 Installation on a PMCspan-002/MVME5100 ...............1-15 Figure 2-1. Boot-Up Sequence ........
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List of Tables Table 1-1. Manually Configured Headers/Jumpers ...................................................1-4 Table 3-1. Debugger Commands .............................................................................3-22 Table 3-2. Diagnostic Test Groups...........................................................................3-27 Table 4-1. MVME5100 General Features..................................................................4-1 Table 5-1. Jumper Switches and Settings..........................
Table C-3. Related Specifications ........................................................................... C-4 Table D-1. RAM500 Feature Summary .................................................................. D-1 Table D-2. RAM500 SDRAM Memory Size Options ............................................ D-3 Table D-3. RAM500 Bottom Side Connector (P1) Pin Assignments ...................................................................................................... D-8 Table D-4.
About This Manual The MVME51xx Single Board Computer Installation and Use provides the information you will need to install and configure your MVME51xx Single Board Computer. It provides specific preparation and installation information and data applicable to the board.
Part Number Description MVME712M Transition module connectors: One DB-25 sync/async serial port, three DB25 async serial ports, one AUI connector, one D-36 parallel port, and one 50pin 8-bit SCSI; includes 3-row DIN P2 adapter module and cable.
Summary of Changes The following changes were made for the 4th revision of this manual. Date Doc. Rev Changes 08/2001 V5100A/IH2 A correction was made on page 1-5 to change the explanation of the jumper settings for Flash Bank A and B. Flash Bank B (0) is the factory setting. Memory Map information was also added to Chapter 6, Programming Information. Appendix B, Specifications was updated, and Appendix D, RAM500 Memory Expansion Module was added. Other corrections were made throughout the manual.
Chapter 2, Operation, provides a description of the operational functions of the MVME5100 including tips on applying power, a description of the switch settings, the status indicators, I/O connectors, and system power up information. Chapter 3, PPCBug Firmware, provides an explanation of the debugger firmware, PPCBug, on the MVME5100.
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represents the carriage return or Enter key. CTRL represents the Control key. Execute control characters by pressing the Ctrl key and the letter simultaneously, for example, Ctrl-d.
1Hardware Preparation and Installation 1 Introduction This chapter provides information on hardware preparation and installation for the MVME5100 Series of Single Board Computers. Note Unless otherwise specified, the designation “MVME5100” refers to all models of the MVME5100-series Single Board Computers. Getting Started The following subsections include information helpful in preparing your equipment.
1 Hardware Preparation and Installation The following equipment list is appropriate for use in an MVME5100 system: ❏ PMCspan PCI expansion mezzanine module (mates with MVME5100) ❏ Peripheral Component Interconnect (PCI) Mezzanine Cards (PMCs) (installed on an MVME5100 board) ❏ RAM500 memory mezzanine modules (installed on an MVME5100 board) ❏ VME system enclosure ❏ System console terminal ❏ Disk drives (and/or other I/O) and controllers ❏ Operating system (and/or application software) Unpack
Preparation protected working surface. Do not slide the component over any surface. In the case of a Printed Circuit Board (PCB), place the board with the component side facing up. If an ESD station is not available, you can avoid damage resulting from ESD by wearing an antistatic wrist strap (available locally) that is attached to an active electrical ground. Note A system chassis may not be a suitable grounding source if it is unplugged.
1 Hardware Preparation and Installation It is important to note that some options are not software-programmable. These specific options are controlled through manual installation or removal of jumpers, and in some cases, the addition of other interface modules on the MVME5100. The following table lists the manually configured jumpers on the MVME5100, and their default settings.
Preparation Table 1-1. Manually Configured Headers/Jumpers (Continued) Jumper Description Setting J15 System Controller (VME) Pins 1, 2 for No SCON Pins 2, 3 for Auto SCON No Jumper for ALWAYS SCON J16 Soldered Flash Protection Pins 1, 2 Enables Programming of Flash Pins 2, 3 Disables Programming of the upper 64KB of Flash Default Auto SCON Flash Prog. Enabled1 Refer to the section titled Jumper Settings on the next page for additional information. Note 1.
1 Hardware Preparation and Installation PMC I/O Mode 2 4 6 SBC I/O Mode J10 2 4 6 1 3 5 2 4 6 1 3 5 J10 1 3 5 2 4 6 1 3 5 J17 J17 J4 J4 123456 7 8 123456 7 8 For rear panel LAN, jumper entire 8 pin header on J4 PMC/SBC (761/IPMC) Mode Selection There are five headers associated with the selection of the PMC or SBC mode: J4, J6 J10, J17 and J20.
Preparation Whether the MVME5100 operates as a VMEbus master or as a VMEbus slave, it is configured for 32 bits of address and 32 bits of data (A32/D32). However, it handles A16 or A24 devices in the appropriate address ranges. D8 and/or D16 devices in the system must be handled by the processor software. If the MVME5100 tries to access off-board resources in a nonexistent location and if the system does not have a global bus time-out, the MVME5100 waits indefinately for the VMEbus cycle to complete.
1 Hardware Preparation and Installation Installation This section discusses the installation of PMCs onto the MVME5100, installation of PMCspan modules onto the MVME5100, and the installation of the MVME5100 into a VME chassis. Note 1-8 If you have ordered one or more of the optional RAM500 memory mezzanine boards for the MVME5100, ensure that they are installed on the board prior to proceeding.
J1 P1 J22 J24 J12 XU1 S1 J11 XU2 J23 L1 J4 J3 J5 U8 HAWK ASIC PCI MEZZANINE CARD J14 J6 J13 J7 J8 J16 J15 LAN 2 J10 J17 BFL CPU P2 LAN 1 ABT/RST 10/100 BASE T10/100 BASE T J20 J25 DEBUG 2788 0700 2788 0700 1-9 http://www.motorola.com/computer/literature J21 L2 PCI MEZZANINE CARD Figure 1-1.
1 Hardware Preparation and Installation PMC Modules PMC modules mount on top of the MVME5100. Perform the following steps to install a PMC module on your MVME5100. Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Warning Caution Inserting or removing modules with power applied may result in damage to module components. Avoid touching areas of integrated circuitry, static discharge can damage these circuits.
Installation Figure 1-2. MVME5100 Installation and Removal From a VMEbus Chassis Figure 1-3. Typical PMC Module Placement on an MVME5100 http://www.motorola.
1 Hardware Preparation and Installation Primary PMCspan To install a PMCspan-002 PCI expansion module on your MVME5100, perform the following steps while referring to the figure on the next page: Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Warning Caution Inserting or removing modules with power applied may result in damage to module components.
Installation 5. Place the PMCspan on top of the MVME5100. Align the mounting holes in each corner to the standoffs and align PMCspan connector P4 with MVME5100 connector J25. PMCspan MVME5100 2081 9708 Figure 1-4. PMCspan-002 Installation on an MVME5100 6. Gently press the PMCspan and MVME5100 together and verify that P4 is fully seated in J25. http://www.motorola.
1 Hardware Preparation and Installation 7. Insert four short screws (Phillips type) through the holes at the corners of the PMCspan and into the standoffs on the MVME5100. Tighten screws securely. Secondary PMCspan The PMCspan-010 PCI expansion module mounts on top of a PMCspan-002 PCI expansion module. To install a PMCspan-010 on your MVME5100, perform the following steps while referring to the figure on the next page: Dangerous voltages, capable of causing death, are present in this equipment.
Installation PMCspan-010 P3 MVME5100 and PMCspan-002 Assembly J3 2065 9708 Figure 1-5. PMCspan-010 Installation on a PMCspan-002/MVME5100 4. Remove four screws (Phillips type) from the standoffs in each corner of the primary PCI expansion module. 5. Attach the four standoffs from the PMCspan-010 mounting kit to the PMCspan-002 by screwing the threaded male portion of the standoffs in the locations where the screws were removed in the previous step. 6. Place the PMCspan-010 on top of the PMCspan-002.
1 Hardware Preparation and Installation 7. Gently press the two PMCspan modules together and verify that P3 is fully seated in J3. 8. Insert the four screws (Phillips type) through the holes at the corners of PMCspan-010 and into the standoffs on the primary PMCspan-002. Tighten screws securely. Note The screws have two different head diameters. Use the screws with the smaller heads on the standoffs next to VMEbus connectors P1 and P2.
Installation 3. Remove the filler panel from the VMEbus chassis card slot where you are going to install the MVME5100. If you have installed one or more PMCspan PCI expansion modules onto your MVME5100, you will need to remove filler panels from one additional card slot for each PMCspan, above the card slot for the MVME5100. – If you intend to use the MVME5100 as system controller, it must occupy the left-most card slot (slot 1).
1 Hardware Preparation and Installation 8. Replace the chassis or system cover(s) and cable peripherals to the panel connectors as required. 9. Reconnect the system to the AC or DC power source and turn the system power on. 10. The MVME5100’s green CPU LED indicates activity as a set of confidence tests is run, and the debugger prompt PPC6-Bug> appears.
2Operation 2 Introduction This chapter provides operating instructions for the MVME5100 Single Board Computer. It includes necessary information about powering up the system along with the functionality of the switches, status indicators, and I/O ports on the front panels of the board.
Operation The on-board Universe ASIC includes both a global and a local reset driver. When the ASIC operates as the System Controller, the reset driver provides a global system reset by asserting the SYSRESET# signal.
System Powerup 10/100 BASE T Ports 2 The two RJ-45 ports labeled 10/100 BASE T provide the 10BaseT/100BaseTX Ethernet LAN interface. These connectors are toplabeled with the designation LAN1 and LAN2. DEBUG Port The RJ-45 port labeled DEBUG provides an RS232 serial communications interface, based on TL16C550 Universal Asynchronous Receiver/Transmitter (UART) controller chip. It is asynchronous only. For additional information on pin assignments, refer to Chapter 5, Pin Assignments.
Operation 2 Initialization Process The MPU, hardware, and firmware initialization process is performed by the PPCBug firmware upon system powerup or system reset. The firmware initializes the devices on the MVME5100 in preparation for booting an operating system. The firmware is shipped from the factory with an appropriate set of defaults. Depending on your system and specific application, there may or may not be a need to modify the firmware configuration before you boot the operating system.
System Powerup 2 Powerup/reset initialization STARTUP Initialize devices on the MVME5100 INITIALIZATION POST PowerOn Self-Test diagnostics Firmware-configured boot mechanism, BOOTING if so configured. Default is no boot. MONITOR Interactive, command-driven on-line PPC debugger, when terminal connected. Figure 2-1. Boot-Up Sequence http://www.motorola.
3PPCBug Firmware 3 Introduction The PPCBug firmware is the layer of software just above the hardware. The firmware provides the proper initialization for the devices on the MVME5100 upon powerup or reset. This chapter describes the basics of the PPCBug and its architecture. It also describes the monitor (interactive command portion of the firmware), and provides information on using the PPCBug debugger and the special commands. A complete list of PPCBug commands is also provided.
PPCBug Firmware ❏ A self-test at powerup feature which verifies the integrity of the system PPCBug consists of three parts: 3 ❏ A command-driven, user-interactive software debugger, described in the PPCBug Firmware Package User’s Manual, listed in Appendix C, Related Documentation (hereafter referred to as “debugger” or “PPCBug”). ❏ A command-driven diagnostics package for the MVME5100 hardware (hereafter referred to as “diagnostics”).
Using PPCBug Implementation and Memory Requirements PPCBug is written largely in the C programming language, providing benefits of portability and maintainability. Where necessary, assembly language has been used in the form of separately compiled program modules containing only assembler code. 3 Physically, PPCBug is contained in two socketed 32-pin PLCC Flash devices that together provide 1MB of storage. The executable code is checksummed at every power-on or reset firmware entry.
PPCBug Firmware For example, if a breakpoint has been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program. Alternately, the user program could return to the debugger by means of the System Call Handler routine RETURN (described in the PPCBug Firmware Package User’s Manual). For more about this, refer to the GD, GO, and GT command descriptions in the PPCBug Firmware Package User’s Manual, listed in Appendix C, Related Documentation .
Using PPCBug 8. Delays for 750 milliseconds. 9. Determines the CPU base board type. 3 10. Sizes the local read/write memory (that is, DRAM). 11. Initializes the read/write memory controller. Sets base address of memory to 0x00000000. 12. Retrieves the speed of read/write memory. 13. Initializes the read/write memory controller with the speed of read/write memory. 14. Retrieves the speed of read only memory (that is, Flash). 15.
PPCBug Firmware 27. Calculates and displays the MPU clock speed, verifies that the MPU clock speed matches the configuration data, and displays a warning message if the verification fails. 3 28. Displays the BUS clock speed, verifies that the BUS clock speed matches the configuration data, and displays a warning message if the verification fails. 29. Probes PCI bus for supported network devices. 30. Probes PCI bus for supported mass storage devices. 31.
Default Settings CNFG - Configure Board Information Block Use this command to display and configure the Board Information Block, which is resident within the NVRAM. This data block contains various elements detailing specific operational parameters of the MVME5100.
PPCBug Firmware Refer to the PPCBug Firmware Package User's Manual for a description of the use of ENV. Additional information on registers in the Universe ASIC that affect these parameters is contained in your MVME5100 Programmer’s Reference Guide, listed in Appendix C, Related Documentation. 3 Listed and described below are the parameters that you can configure using ENV. The default values shown were those in effect when this publication went to print.
Default Settings Note: The bug does not automatically acquire all of the memory it is allowed. It accumulates memory as necessary in one megabyte blocks. 3 Field Service Menu Enable [Y/N] = N? Y Display the field service menu. N Do not display the field service menu. (Default) Remote Start Method Switch [G/M/B/N] = B? The Remote Start Method Switch is used when the MVME5100 is crossloaded from another VME-based CPU in order to start execution of the cross-loaded program.
PPCBug Firmware Auto-Initialize of NVRAM Header Enable [Y/N] = Y? Y NVRAM (PReP partition) header space will be initialized automatically during board initialization, but only if the PReP partition fails a sanity check. (Default) N NVRAM header space will not be initialized automatically during board initialization. 3 Network PReP-Boot Mode Enable [Y/N] = N? Y Enable PReP-style network booting (same boot image from a network interface as from a mass storage device).
Default Settings Primary SCSI Data Bus Width [W/N] = N? W Wide SCSI (16-bit bus). N Narrow SCSI (8-bit bus). (Default) 3 Secondary SCSI identifier = 07? Select the identifier. (Default = 07.) NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N? Note Y Give boot priority to devices defined in the fw-bootpath global environment variable (GEV). N Do not give boot priority to devices listed in the fwboot-path GEV.
PPCBug Firmware Auto Boot at powerup only [Y/N] = N? 3 Y Autoboot is attempted at powerup reset only. N Autoboot is attempted at any reset. (Default) Auto Boot Scan Enable [Y/N] = Y? Y If Autoboot is enabled, the Autoboot process attempts to boot from devices specified in the scan list (for example, FDISK/CDROM/TAPE/HDISK). (Default) N If Autoboot is enabled, the Autoboot process uses the Controller LUN and Device LUN to boot.
Default Settings Auto Boot Abort Delay = 7? The time in seconds that the Autoboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key. The time value is from 0-255 seconds. (Default = 7 seconds) Auto Boot Default String [NULL for an empty string] = ? You may specify a string (filename) which is passed on to the code being booted. The maximum length of this string is 16 characters.
PPCBug Firmware ROM Boot Direct Ending Address = FFFFFFFC? The last location tested when PPCBug searches for a ROMboot module. (Default = 0xFFFFFFFC) 3 Network Auto Boot Enable [Y/N] = N? Y The Network Auto Boot (NETboot) function is enabled. N The NETboot function is disabled. (Default) Network Auto Boot at power-up only [Y/N] = N? Y NETboot is attempted at powerup reset only. N NETboot is attempted at any reset.
Default Settings ! Caution If you use the NIOT debugger command, these parameters need to be saved somewhere in the offset range 0x00001000 through 0x000016F7. The NIOT parameters do not exceed 128 bytes in size. The setting of this ENV pointer determines their location. If you have used the same space for your own program information or commands, they will be overwritten and lost.
PPCBug Firmware ROM Bank B Access Speed (ns) = 70? This defines the minimum access speed for the Bank B Flash Device(s) in nanoseconds. 3 DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O? Note O DRAM parity is enabled upon detection. (Default) A DRAM parity is always enabled. N DRAM parity is never enabled. This parameter also applies to enabling ECC for DRAM. L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O? O L2 Cache parity is enabled upon detection.
Default Settings Serial Startup Code LF Enable [Y/N]=N? A line feed can be inserted after each code is displayed to prevent it from being overwritten by the next code. This is also enabled by an ENV parameter: The list of LED/serial codes is included in the section on MPU, Hardware, and Firmware Initialization found in Chapter 1 of the PPCBug Firmware Package User’s Manual, listed in Appendix C, Related Documentation.
PPCBug Firmware The configured value is written into the LSI0_TO register of the Universe chip. PCI Slave Image 1 Control = C0820000? 3 The configured value is written into the LSI1_CTL register of the Universe chip. PCI Slave Image 1 Base Address Register = 81000000? The configured value is written into the LSI1_BS register of the Universe chip. PCI Slave Image 1 Bound Address Register = A0000000? The configured value is written into the LSI1_BD register of the Universe chip.
Default Settings The configured value is written into the LSI3_BS register of the Universe chip. PCI Slave Image 3 Bound Address Register = B0000000? The configured value is written into the LSI3_BD register of the Universe chip. PCI Slave Image 3 Translation Offset = 50000000? The configured value is written into the LSI3_TO register of the Universe chip. VMEbus Slave Image 0 Control = E0F20000? The configured value is written into the VSI0_CTL register of the Universe chip.
PPCBug Firmware VMEbus Slave Image 1 Translation Offset = 00000000? The configured value is written into the VSI1_TO register of the Universe chip. 3 VMEbus Slave Image 2 Control = 00000000? The configured value is written into the VSI2_CTL register of the Universe chip. VMEbus Slave Image 2 Base Address Register = 00000000? The configured value is written into the VSI2_BS register of the Universe chip.
Default Settings Special PCI Slave Image Register = 00000000? The configured value is written into the SLSI register of the Universe chip. Master Control Register = 80C00000? 3 The configured value is written into the MAST_CTL register of the Universe chip. Miscellaneous Control Register = 52060000? The configured value is written into the MISC_CTL register of the Universe chip. User AM Codes = 00000000? The configured value is written into the USER_AM register of the Universe chip.
PPCBug Firmware The string 'NULL' on a new line terminates the command line entries. All PPCBug commands, except for the following, may be used within the command buffer: DU, ECHO, LO, TA, VE. 3 Note Interactive editing of the startup command buffer is not supported. If changes are needed to an existing set of startup commands, a new set of commands with changes must be reentered. Standard Commands The individual debugger commands are listed in the following table.
Standard Commands Table 3-1.
PPCBug Firmware Table 3-1.
Standard Commands Table 3-1.
PPCBug Firmware Table 3-1.
Standard Commands PPCBug Diagnostics Manual, listed in Appendix C, Related Documentation for complete descriptions of the diagnostic routines and instructions on how to invoke them. 3 Table 3-2.
4Functional Description 4 Introduction This chapter provides a functional description for the MVME5100 Single Board Computer. The MVME5100 is a high-performance product featuring Motorola’s PowerPlus II architecture with a choice of PowerPC processors—either Motorola’s MPC7410 with AltiVec™ technology for algorithmic intensive computations or the low-power MPC755 or MPC750.
Functional Description Table 4-1. MVME5100 General Features (Continued) Feature L2 Cache (Optional) 1MB (MPC750 or MPC755) or 2MB (MPC7410) using burst-mode SRAM modules.
Features Descriptions Features Descriptions General As stated earlier, the MVME5100 is a high-performance VME based Single Board Computer featuring Motorola’s PowerPlus II architecture with a choice of processors. The board can be equipped with either the Motorola MPC7410 processor with AltiVec™ technology for algorithmic intensive computations or with the low-power MPC755 or MPC750 for low-power or field applications.
Functional Description The following diagram illustrates the architecture of the MVME5100 Single Board Computer.
Features Descriptions Processor The MVME5100 incorporates a BGA foot print that supports both the MCP7410 and the MCP75x processors. The maximum external processor bus speed is 100 MHz. Note The MCP7410 is configured to operate only with the PowerPC 60xbus interface. System Memory Controller and PCI Host Bridge The on-board Hawk ASIC provides the bridge function between the processor’s bus and the PCI bus.
Functional Description Application Note: For Am29DL322C or Am29DL323C, 32Megabit (4M x 8-Bit/2M x 16-bit) CMOS 3.0 Volt-only Flash Memory. The Write Protect function provides a hardware method of protecting certain boot sectors.
Features Descriptions P2 Input/Output (I/O) Modes The MVME5100 has two P2 I/O modes (SBC and PMC) that are userconfigurable with jumpers on the board (J6 and J20). The jumpers route the on-board Ethernet port 2 to row C of the P2 connector. Ethernet jumpers (J4, J10, and J17) should also be configured. The SBC mode (also called 761 or IPMC mode) are backwards compatible with the corresponding MVME712 and MVME761 transition cards and the P2 adapter card (excluding PMC I/O routing) used on the MVME2600/2700.
Functional Description Every board is assigned two Ethernet Station Addresses. The address is $0001AFXXXXX where XXXXX is the unique number assigned to each interface. Each Ethernet Station Address is displayed on a label attached to the PMC front-panel keep-out area. In addition, LAN 1 Ethernet address is stored in the configuration area of the NVRAM specified by the Boot ROM and in SROM. 4 VMEbus Interface The VMEbus interface is provided by the Universe II ASIC.
Features Descriptions This is accomplished by using the corresponding on-board IPMC712 or IPMC761 connector to route the PCI/ISA Bridge interrupt signal to the external interrupt 0 of the Hawk ASIC (MPIC). Note The SCSI device on either the IPMC712 or IPMC761 uses the standard INTA# pin J11-04 of PMC Slot 1. IDSEL Routing Legacy IDSEL assignment for the PCI/ISA Bridge is also maintained to ensure software compatibility between MVME5100 and the MVME2700 while in SBC mode (also called 761 or IPMC mode).
5Pin Assignments 5 Introduction This chapter provides information on pin assignments for various jumpers and connectors on the MVME5100 Single Board Computer.
Pin Assignments Jumper Settings The following table provides information about the jumper settings associated with th MVME5100 Single Board Computer. The table below provides a brief description of each jumper and the appropriate setting(s) for proper board operation. Table 5-1.
Connectors Connectors IPMC761 Connector (J3) Pin Assignments This connetor is used to provide an interface to the IPMC761 module signals and is located near J11. The pin assignments for this connector are as follows: Table 5-2. IPMC761 Connector Pin Assignments Pin Assignment Pin 1 I2CSCL I2CSDA 2 3 GND GND 4 5 DB8# GND 6 7 GND DB9# 8 9 DB10# +3.3V 10 11 +3.3V DB11# 12 13 DB12# GND 14 15 GND DB13# 16 17 DB14# +3.3V 18 19 +3.
Pin Assignments Memory Expansion Connector (J8) Pin Assignments This connector is used to provide memory expansion capability. A single memory mezzanine card provides a maximum of 256MB of memory. Attaching another memory mezzanine to the first mezzanine provides an additional 512MB of expansion memory. The pin assignments for this connector are as follows: Table 5-3.
Connectors Table 5-3. Memory Expansion Connector Pin Assignments (Continued) Pin Assignment Pin 47 DQ36 DQ37 48 49 DQ38 DQ39 50 51 +3.3V +3.3V 52 53 DQ40 DQ41 54 55 DQ42 DQ43 56 57 DQ44 DQ45 58 59 DQ46 DQ47 60 61 GND GND 62 63 DQ48 DQ49 64 65 DQ50 DQ51 66 67 DQ52 DQ53 68 69 +3.3V +3.
Pin Assignments Table 5-3. Memory Expansion Connector Pin Assignments (Continued) Pin 5 Pin 105 A04 A03 106 107 A02 A01 108 109 +3.3V +3.3V 110 111 A00 CS_C0_L 112 113 CS_E0_L GND 114 115 CS_C1_L CS_E1_L 116 117 WE_L RAS_L 118 119 GND GND 120 121 CAS_L +3.3V 122 123 +3.3V DQMB0 124 125 DQMB1 SCL 126 127 SDA A1_SPD 128 129 A0_SPD MEZZ1_L 130 131 MEZZ2_L GND 132 133 GND SDRAMCLK1 134 135 SDRAMCLK3 +3.
Connectors PCI Expansion Connector (J25) Pin Assignments This connector is used to provide PCI/PMC expansion capability. The pin assignments for this connector are as follows: Table 5-4. PCI Expansion Connector Pin Assignments Pin Assignment 1 +3.3V +3.
Pin Assignments Table 5-4.
Connectors Table 5-4.
Pin Assignments PCI Mezzanine Card (PMC) Connectors These connectors provide 32/64-bit PCI interfaces and P2 I/O for two optional add-on PCI Mezzanine Cards (PMC). The pin assignments for these connectors are as follows. Table 5-5.
Connectors Table 5-5. PMC Slot 1 Connector (J11) Pin Assignments (Continued) Pin Assignment Pin 49 AD09 +5V 50 51 GND C/BE0# 52 53 AD06 AD05 54 55 AD04 GND 56 57 +5V (Vio) AD03 58 59 AD02 AD01 60 61 AD00 +5V 62 63 GND REQ64# 64 http://www.motorola.
Pin Assignments Table 5-6. PMC Slot 1 Connector (J12) Pin Assignments Pin 5 5-12 Assignment Pin 1 +12V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull-up to +3.3V +3.3V 12 13 RST# Pull-down to GND 14 15 +3.3V Pull-down to GND 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 +3.3V 24 25 IDSEL1 AD23 26 27 +3.3V AD20 28 29 AD18 GND 30 31 AD16 C/BE2# 32 33 GND Not Used 34 35 TDRY# +3.
Connectors Table 5-6. PMC Slot 1 Connector (J12) Pin Assignments (Continued) Pin Assignment Pin 59 GND Not Used 60 61 ACK64# +3.3V 62 63 GND Not Used 64 5 Table 5-7.
Pin Assignments Table 5-7.
Connectors Table 5-8.
Pin Assignments Table 5-8. PMC Slot 1 Connector (J14) Pin Assignments (Continued) Pin 5 Assignment Pin 53 PMC1_53 (P2-C27) PMC1_54 (P2-A27) 54 55 PMC1_55 (P2-C28) PMC1_56 (P2-A28) 56 57 PMC1_57 (P2-C29) PMC1_58 (P2-A29) 58 59 PMC1_59 (P2-C30) PMC1_60 (P2-A30) 60 61 PMC1_61 (P2-C31) PMC1_62 (P2-A31) 62 63 PMC1_63 (P2-C32) PMC1_64 (P2-A32) 64 Jumper configuration is dependent upon P2 I/O mode chosen (PMC or SBC Mode, also known as 761 or IPMC mode).
Connectors Table 5-9.
Pin Assignments Table 5-9. PMC Slot 2 Connector (J21) Pin Assignments (Continued) Pin 5 Assignment Pin 49 AD09 +5V 50 51 GND C/BE0# 52 53 AD06 AD05 54 55 AD04 GND 56 57 +5V (Vio) AD03 58 59 AD02 AD01 60 61 AD00 +5V 62 63 GND REQ64# 64 Table 5-10. PMC Slot 2 Connector (J22) Pin Assignments Pin 5-18 Assignment Pin 1 +12V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull-up to +3.3V +3.
Connectors Table 5-10. PMC Slot 2 Connector (J22) Pin Assignments (Continued) Pin Assignment Pin 23 AD24 +3.3V 24 25 IDSEL2 AD23 26 27 +3.3V AD20 28 29 AD18 GND 30 31 AD16 C/BE2# 32 33 GND Not Used 34 35 TDRY# +3.3V 36 37 GND STOP# 38 39 PERR# GND 40 41 +3.3V SERR# 42 43 C/BE1# GND 44 45 AD14 AD13 46 47 GND AD10 48 49 AD08 +3.3V 50 51 AD07 Not Used 52 53 +3.
Pin Assignments Table 5-11.
Connectors Table 5-11. PMC Slot 2 Connector (J23) Pin Assignments (Continued) Pin Assignment Pin 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 +5V (Vio) AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 63 GND Reserved 64 5 Table 5-12.
Pin Assignments Table 5-12.
Connectors VMEbus Connectors P1 & P2 Pin Assignments (PMC mode) The VMEbus connector P1 provides power and VME signals for 24-bit address and 16-bit data. The pin assignments for the connector are specified by the IEEE P1014-1987 VMEbus Specification and the VME64 Extension Standard. Row B of connector P2 provides power to the MVME5100, and to the upper eight VMEbus address lines, and additional 16 VMEbus data lines. Rows A, C, Z, and D provide power and interface signals to the MVME762 transition module.
Pin Assignments Table 5-13.
Connectors VMEbus P1 & P2 Connector Pin Assignments (SBC Mode) The VMEbus connector P1 provides power and VME signals for 24-bit address and 16-bit data. The pin assignments for the connector are specified by the IEEE P1014-1987 VMEbus Specification and the VME64 Extension Standard. Row B of connector P2 provides power to the MVME5100 and to the upper 8 VMEbus address lines and additional 16 VMEbus data lines.
Pin Assignments Table 5-14.
Connectors Note Rows A and C and Z’s (Z1, 3, 5 , 7, 9, 11, 13, 15, and 17) functionality is provided by the IPMC761 in slot 1 and the MVME5100 Ethernet port 2. Table 5-15.
Pin Assignments Table 5-15.
Connectors 10 BaseT/100 BaseTx Connector Pin Assignments The board’s dual 10 BaseT/100 BaseTx RJ45 connectors (J9 and J18) are located on the front plate. The connections provide two LAN connections (LAN1-J18 and LAN2-J9). The pin assignments for these connector’s are as follows: Table 5-16. 10 BaseT/100 BaseTx Connector Pin Assignment Pin 5 Assignment 1 TD+ 2 TD- 3 RD+ 4 AC Terminated 5 AC Terminated 6 RD- 7 AC Terminated 8 AC Terminated http://www.motorola.
Pin Assignments COM1 and COM2 Connector Pin Assignments A standard RJ45 connector located on the front panel and a 9-pin header located near the bottom edge of the MVME5100 provides the interface to the serial debug ports. The RJ45 connector is for COM1 and the 9-pin header is for COM2. The pin assignments for these connectors are as follows: 5 Table 5-17. COM1 (J19) Connector Pin Assignments Pin Assignment 1 DCD 2 RTS 3 GNDC 4 TXD 5 RXD 6 GNDC 7 CTS 8 DTR Table 5-18.
6Programming the MVME51xx 6 Introduction This chapter provides basic information useful in programming the MVME51xx. This includes a description of memory maps, control and status registers, PCI arbitration, interrupt handling, sources of reset, and big/little-endian issues. For additional programming information about the MVME510x, refer to the MVME5100-Series Single Board Computer Programmer’s Reference Guide.
Programming the MVME51xx Processor Bus Memory Map The processor memory map configuration is under the control of the PHB and SMC portions of the Hawk ASIC. The Hawk adjusts system mapping to suit a given application via programmable map decoder registers. At system power-up or reset, a default processor memory map takes over. Default Processor Memory Map The default processor memory map that is valid at power-up or reset remains in effect until reprogrammed for specific applications.
Memory Maps For an example of the CHRP memory map, refer to the following table. For detailed processor memory maps, including suggested CHRP- and PREPcompatible memory maps, refer to the MVME5100-Series Single Board Computer Programmer’s Reference Guide. Processor Memory Map The following table describes a suggested CHRP Memory Map from the point of view of the processor. This memory map is an alternative to the PREP memory map.
Programming the MVME51xx Table 6-2. Suggested CHRP Memory Map (Continued) Processor Address Start Size Definition Notes End FF00 0000 FF7F FFFF 8MB FLASH Bank A (preferred) 1, 2 FF80 0000 FF8F FFFF 1MB FLASH Bank B (preferred) 1, 2 FF90 0000 FFEF FFFF 6MB Reserved FFF0 0000 FFFF FFFF 1MB Boot ROM 3 Notes 6 1. Programmable via Hawk ASIC. 2. The actual Power Plus II size of each ROM/FLASH bank may vary. 3.
Memory Maps Table 6-3. Hawk PPC Register Values for Suggested Memory Map (Continued) Address Register Name Register Name FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 & MSATT2 0000 0000 FEFF 0058 MSADD3 0000 0000 FEFF 005C MSOFF3 & MSATT3 0000 0000 PCI Memory Map Following a reset, the Hawk ASIC disables all PCI slave map decoders. The MVME5100 is fully capable of supporting both PREP and CHRP PCI Memory Maps with RAM size limited to 2GB.
Programming the MVME51xx VMEbus Memory Map The VMEbus is programmable. Like other parts of the MVME510x memory map, the mapping of local resources as viewed by VMEbus masters varies among applications. The Universe PCI/VME bus bridge ASIC includes a user-programmable map decoder for the VMEbus-to-local-bus interface. The address translation capabilities of the Universe enable the processor to access any range of addresses on the VMEbus.
Programming Considerations ❏ PMC Slot 2 (PCI mezzanine card) ❏ PCI Expansion Slot The Winbond W83C554 PIB device supplies the PCI arbitration support for these seven types of devices. The PIB supports flexible arbitration modes of fixed priority, rotating priority, and mixed priority, as appropriate in a given application. Details on PCI arbitration can be found in the MVME5100-Series Single Board Computer Programmer’s Reference Guide. 6 http://www.motorola.
Programming the MVME51xx PROCESSOR VMEBUS PCI MEMORY ONBOARD MEMORY PROGRAMMABLE SPACE 6 NOTE 2 PCI MEMORY SPACE NOTE 1 VME A24 VME A16 NOTE 3 VME A24 VME A16 NOTE 1 VME A24 PCI/ISA MEMORY SPACE VME A16 PCI I/O SPACE VME A24 VME A16 MPC RESOURCES NOTES: 1. Programmable mapping done by Hawk ASIC. 2. Programmable mapping performed via PCI Slave images in Universe ASIC. 3. Programmable mapping performed via Special Slave image (SLSI) in Universe ASIC. 11553.00 9609 Figure 6-1.
Programming Considerations The arbitration assignments for the MVME510x are shown in Table 6-4. Table 6-4. PCI Arbitration Assignments PCI Bus Request PCI Master(s) PIB (Internal) PIB CPU Hawk ASIC Request 0 PMC Slot 2 Request 1 PMC Slot 1 Request 2 PCI Expansion Slot Request 3 Ethernet Request 4 Universe ASIC (VMEbus) 6 Interrupt Handling The Hawk ASIC, which controls the PHB (PCI Host Bridge) and the MPU/local bus interface functions on the MVME510x, performs interrupt handling as well.
Programming the MVME51xx INT INT_ PIB (8529 Pair) Processor 6 MCP_ Hawk MPIC SERR_& PERR_ PCI Interrupts ISA Interrupts 11559.00 9609 Figure 6-2.
Programming Considerations The MVME510x routes the interrupts from the PMCs and PCI expansion slots as follows: PMC Slot 1 INTA# INTB# INTC# INTD# PMC Slot 2 INTA# INTB# INTC# INTD# PCIX Slot INTA# INTB# INTC# INTD# 6 IRQ9 IRQ10 IRQ11 IRQ12 Hawk MPIC DMA Channels The PIB supports seven DMA channels. They are not functional on the MVME510x. Sources of Reset The MVME510x has nine potential sources of reset: 1. Power-on reset 2. RST switch (resets the VMEbus when the MVME510x is system controller) 3.
Programming the MVME51xx 5. PCI/ISA I/O Reset function controlled by the Clock Divisor register in the PIB 6. The VMEbus SYSRESET∗ signal 7. VMEbus Reset sources from the Universe ASIC (PCI/VME bus bridge controller): the System Software reset, Local Software Reset, and VME CSR Reset functions. Note 6 On the MVME5100, Watchdog Timer 2 is a source of reset only if component R206 is installed on the board.
Programming Considerations Endian Issues The MVME510x supports both little-endian (e.g., Windows NT) and bigendian (e.g., AIX) software. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little-endian. The following sections summarize how the MVME510x handles software and hardware differences in big- and little-endian operations. For further details on endian considerations, refer to the MVME5100-Series Single Board Computer Programmer’s Reference Guide.
Programming the MVME51xx endian mode, no endian issues should arise for Ethernet data. Big-endian software must still take the byte-swapping effect into account when accessing the registers of the PCI/Ethernet device, however.
ASpecifications A This appendix lists general specifications and power characteristics for the MVME5100 Single Board Computer. It also provides information on cooling requirements. A complete functional description of the MVME5100 Single Board Computer appears in Chapter 4, Functional Description. Specifications for the optional PMC modules can be found in the documentation for those modules. General Specifications The following table lists general specifications for MVME5100 Single Board Computer.
A Specifications Power Requirements Power requirements for the MVME5100 Single Board Computer depend on the configuration of the board. The table below lists the typical and maximum power consumption of the board using an MVME761 Transition Module. Table A-2. Power Consumption Model +5V +/-5% +12V +/-10% -12V +/-10% MVME5100 3.8A max 3.0A typ. 8.0 mA typ. 2.0 mA typ. MVME5106 3.8A max 2.6A typ 8.0 mA typ 2.0 mA typ. MVME5107 4.7 A max. 3.5 A typ. 8.0 mA typ 2.0 mA typ MVME5110-21xx 3.
Cooling Requirements Cooling Requirements Refer to Appendix E, "Thermal Requirements" for more information. EMC Compliance The MVME5100 was tested in an EMC-compliant chassis and meets the requirements for EN55022 Class B equipment. Compliance was achieved under the following conditions: ❏ Shielded cables on all external I/O ports ❏ Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel ❏ Conductive chassis rails connected to earth ground.
BTroubleshooting B Solving Startup Problems In the event of difficulty with your MVME5100, perform the simple troubleshooting steps listed in the table below before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment. It is important to note that the Board was tested under these conditions before it left the factory. The self-tests may not run in all usercustomized environments. Table B-1.
Solving Startup Problems Table B-1. Troubleshooting Problems (Continued) B Condition Possible Problem II. There is a display A. The keyboard or on the terminal; mouse may be however, keyboard connected and/or mouse input incorrectly. has no effect. B. Board jumpers may be configured incorrectly. Possible Resolution: Recheck the keyboard connections and power. Verify correct configuration of RS232 interface. Check the board jumpers per the instructions in this manual. C.
Troubleshooting Table B-1. Troubleshooting Problems (Continued) Condition IV. Debug prompt PPC6-Bug> appears at powerup; the board does not autoboot (Continued) Possible Problem B Possible Resolution: 2. At the command line prompt, type in: env;d (this sets up the default parameters for the debugger environment). 3. When prompted to Update Non-Volatile RAM, type in: y 4. When prompted to Reset Local System, type in: y 5.
Solving Startup Problems Table B-1. Troubleshooting Problems (Continued) B Condition Possible Problem V. The debugger is in A. No apparent system mode; the problems — board autoboots, troubleshooting is or the board has done. passed self tests. Possible Resolution: No further troubleshooting steps are required. VI. The board has A. There may be 1. Document the problem and return the board for service. failed one or more some fault in the 2. Phone 1-800-222-5640.
CRelated Documentation C Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: ❏ Contacting your local Motorola sales office ❏ Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature Table C-1.
Manufacturers’ Documents Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As an additional help, a source for the listed document is provided. Please note that while these sources have been verified, the information is subject to change without notice. C Table C-2.
Related Documentation Table C-2. Manufacturers’ Documents (Continued) Document Title 2-Wire Serial CMOS EEPROM Data Sheet Atmel Corporation San Jose, CA Intel GD82559ER Fast Ethernet PCI Controller Datasheet Intel Corporation http://www.motorola.com/computer/literature Publication Number C AT24C04 714682-001 Rev. 1.
Related Specifications Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice. C Table C-3. Related Specifications Publication Number Document Title and Source Peripheral Component Interconnect (PCI) Interface Specification, Revision 2.1 PCI Special Interest Group P.O.
DRAM500 Memory Expansion Module D Overview The RAM500 memory expansion module can be used on the MVME5100 as an option for additional memory capability. Each expansion module is a single bank of SDRAM with up to 256MB of available ECC memory. Currently, two expansion modules can be used in tandum to produce an additional expanded memory capability of 512MB. There are two configurations of the board to accommodate tandum usage.
Functional Description Functional Description The following sections describe the physical and electrical structure of the RAM500 memory expansion module. D RAM500 Description The RAM500 is a memory expansion module that is used on the MVME5100 Single Board Computer, and will be used on other Motorola products in the future.
RAM500 Memory Expansion Module When populated, the optional RAM500 memory expansion memory blocks should appear as Block C and Block E to the Hawk ASIC. Block C and E are used because each of the module’s SPD is defined to correspond to two banks of memory each: C and D for the first SPD and E and F for the second SPD. The RAM500 SPD uses the SPD JEDEC standard definition and is accessed at address $AA or $AC. Refer to the following section on SROM for more details. Table D-2.
Functional Description A, BA, WE_L, RAS_L, CAS_L, DQ, CKD DQMB0 CS_C_L SCL SDA A0_SPD CLK1,2 Top-side MVME5100-MEZ Connector D CLK3,4 DQMB1 CS_E_L CLK1,2 1 Bank of 9 (x8) SDRAMS SROM SPD Buffer LVTH162244 A, BA, WE_L, RAS_L, CAS_L, DQMB0 CS_C_L DQMB1 CS_E_L DQ, CKD SCL A1_SPD SDA CLK1,2,3,4 Bottom-side MVME5100-MEZ Connector Note: DQMB1, CS_E_L, A1_SPD,CLK3,4 from Bottom Connector is routed to Top connector at the DQMB0, CS_C_L and A0_SPD,CLK1,2 pins. Figure D-1.
RAM500 Memory Expansion Module SROM The RAM500 memory expansion module contains a single 3.3V, 256 x 8, Serial EEPROM device (AT24C02). The Serial EEPROM provides Serial Presence Detect (SPD) storage of the module memory subsystem configuration. The RAM500 SPD is software addressable by a unique address as follows: The first RAM500 attached to the host board has its SPD addressable at $AA. The second RAM500 attached to the host board has its SPD addressable at $AC.
RAM500 Module Installation that standoffs are installed in the three mounting holes on the module. 5. With standoffs installed in the three mounting holes on the RAM500 module, align the standoffs and the P1 connector on the module with the three holes and the J16 connector on the MVME5100 host board and press the two connectors together until they are firmly seated in place. D Figure D-2. RAM500 Module Placement on MVME5100 6.
RAM500 Memory Expansion Module 8. Turn the entire assembly over, and fasten the three nuts provided to the standoff posts on the bottom of the MVME5100 host board. 9. Reinstall the MVME5100 assembly in its proper card slot. Be sure the host board is well seated in the backplane connectors. Do not damage or bend connector pins. 10. Replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on.
RAM500 Connectors Table D-3. RAM500 Bottom Side Connector (P1) Pin Assignments D D-8 1 GND* GND* 2 3 DQ00 DQ01 4 5 DQ02 DQ03 6 7 DQ04 DQ05 8 9 DQ06 DQ07 10 11 +3.3V +3.3V 12 13 DQ08 DQ09 14 15 DQ10 DQ11 16 17 DQ12 DQ13 18 19 DQ14 DQ15 20 21 GND* GND* 22 23 DQ16 DQ17 24 25 DQ18 DQ19 26 27 DQ20 DQ21 28 29 DQ22 DQ23 30 31 +3.3V +3.
RAM500 Memory Expansion Module Table D-3. RAM500 Bottom Side Connector (P1) Pin Assignments (Continued) 63 DQ48 DQ49 64 65 DQ50 DQ51 66 67 DQ52 DQ53 68 69 +3.3V +3.3V 70 71 DQ54 DQ55 72 73 DQ56 DQ57 74 75 DQ58 DQ59 76 77 DQ60 DQ61 78 79 GND* GND* 80 81 DQ62 DQ63 82 83 CKD00 CKD01 84 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 +3.3V +3.
RAM500 Connectors Table D-3. RAM500 Bottom Side Connector (P1) Pin Assignments (Continued) 125 D DQMB1 SCL 126 127 SDA A1_SPD 128 129 A0_SPD MEZZ1_L 130 131 MEZZ2_L GND 132 133 GND SDRAMCLK1 134 135 SDRAMCLK3 +3.3V 136 137 SDRAMCLK4 SDRAMCLK2 138 139 GND* GND* 140 *Common GND pins mate to a GIGA assembly with a ground plate.
RAM500 Memory Expansion Module Table D-4. RAM500 Top Side Connector (J1) Pin Assignments (Continued) 13 DQ08 DQ09 14 15 17 DQ10 DQ11 16 DQ12 DQ13 18 19 DQ14 DQ15 20 21 GND* GND* 22 23 DQ16 DQ17 24 25 DQ18 DQ19 26 27 DQ20 DQ21 28 29 DQ22 DQ23 30 31 +3.3V +3.3V 32 33 DQ24 DQ25 34 35 DQ26 DQ27 36 37 DQ28 DQ29 38 39 DQ30 DQ31 40 41 GND* GND* 42 43 DQ32 DQ33 44 45 DQ34 DQ35 46 47 DQ36 DQ37 48 49 DQ38 DQ39 50 51 +3.3V +3.
RAM500 Connectors Table D-4. RAM500 Top Side Connector (J1) Pin Assignments (Continued) 75 D DQ58 76 77 DQ60 DQ61 78 79 GND* GND* 80 81 DQ62 DQ63 82 83 CKD00 CKD01 84 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 +3.3V +3.3V 90 91 CKD06 CKD07 92 93 BA1 BA0 94 95 A12 A11 96 97 A10 A09 98 99 GND* GND* 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 +3.3V +3.
RAM500 Memory Expansion Module Table D-4. RAM500 Top Side Connector (J1) Pin Assignments (Continued) 133 GND SDRAMCLK3 134 135 +3.3V 136 137 SDRAMCLK4 138 GND* 140 139 GND* D *Common GND pins mate to GIGA assemblies with ground plates. RAM500 Programming Issues The RAM500 contains no user programmable registers, other than the Serial Presence Detect (SPD) Data.
EThermal Analysis E Ambient temperature, air flow, board electrical operation, and software operation affect board component temperatures. To evaluate the thermal performance of a circuit board assembly, you should test the board under actual operating conditions. These operating conditions vary depending on system design. Motorola Computer Group performs thermal analysis in a representative system to verify operation within specified ranges. Refer to Specifications, Table A-1.
Thermal Analysis The preferred temperature measurement location for a component may be: E ❏ junction - refers to the temperature measured by an on-chip thermal device ❏ case - refers to the temperature at the top, center surface of the component ❏ air - refers to the ambient temperature near the component Table E-1.
Thermally Significant Components Table E-2.
Thermal Analysis J1 P1 J6 J14 J5 J12 J3 J24 J13 J4 J22 J11 XU1 S1 J23 XU2 J21 L1 U8 HAWK ASIC PCI MEZZANINE CARD J8 J7 J16 J15 LAN 2 J10 J17 BFL CPU P2 LAN 1 ABT/RST 10/100 BASE T10/100 BASE T J20 J25 DEBUG 2788 0700 Computer Group Literature Center Web Site E-4 L2 PCI MEZZANINE CARD E Figure E-1.
Thermally Significant Components P15 P14 P12 P13 P11 E C10 C8 C7 S1 C9 U12 U11 U7 J3 C5 U6 U5 J2 U4 U3 U19 Y2 U2 Y1 C4 Y3 C2 j1 DS2 DS1 IPMC761 PIB BUSY SCSI BUSY 2844 1100 IPMC761 Figure E-2. Thermally Significant Components on the IPMC761 Module Primary Side http://www.motorola.
Thermal Analysis Component Temperature Measurement This section outlines general temperature measurement methods. For the specific types of measurements required for thermal evaluation of this board, see Table E-1. Preparation We recommend 40-gage thermocouples for all thermal measurements. Larger gage thermocouples can wick heat away from the components and disturb air flowing past the board. E Allow the board to reach thermal equilibrium before taking measurements.
Component Temperature Measurement Note Machining a heatsink base reduces the contact area between the heatsink and the electrical component. You can partially compensate for this effect by filling the machined areas with thermal grease. The grease should not contact the thermocouple junction. E http://www.motorola.
Thermal Analysis Machined groove for thermocouple wire routing E Thermocouple junction bonded to component ISOMETRIC VIEW Machined groove for thermocouple wire routing Through hole for thermocouple junction clearance (may require removal of fin material) Also use for alignment guidance during heatsink installation Thermal pad Heatsink base HEATSINK BOTTOM VIEW Figure E-3.
Component Temperature Measurement Measuring Local Air Temperature Measure local component ambient temperature by placing the thermocouple downstream of the component. This method is conservative since it includes heating of the air by the component. Figure E-4 shows one method of mounting the thermocouple. Tape thermocouple wire to top of component E Thermocouple junction Air flow PWB Figure E-4. Measuring Local Air Temperature http://www.motorola.
Index A Abort (interrupt) signal 2-1 ABT switch (S1) 2-1 AltiVec™ technology 4-3 assembly language 3-3 Asynchronous Communications 4-8 Auto Boot Abort Delay 3-13 Auto Boot Controller 3-12 Auto Boot Default String 3-13 Auto Boot Device 3-12 Auto Boot Partition Number 3-12 Autoboot enable 3-11, 3-12 B backplane connectors, P1 and P2 as power source 1-6 jumpers 1-17 baud rate 2-3 BFL LED 2-2 BG and IACK signals 1-17 bit size data/address (MVME5100) 1-7 bits per character 2-3 board information block 3-6, 3-7
Index DECchip 21143 LAN controller 6-6 diagnostics directory 3-26 hardware 3-26 prompt 3-2 test groups 3-27 dimensions, MVME5100 A-1 directories, debugger and diagnostic 3-26 DMA channels 6-11 DRAM speed 3-15 E I N D E X ECC memory 4-6 ECC SDRAM Memor 4-6 EEPROM 4-2 endian issues function of Hawk ASIC 6-13 function of Universe ASIC 6-14 PCI domain 6-13 processor/memory domain 6-13 VMEbus domain 6-14 ENV Auto Boot Abort Delay 3-13 Auto Boot Controller 3-12 Auto Boot Default String 3-13 Auto Boot Device 3
I I/O modes described (PMC and SBC) 4-3 IACK and BG signals 1-17 IDSEL routing 4-9 initialization performed by PPCBug 2-4 initialization process as performed by firmware 3-4 Input/Output Interface 4-7 installation RAM500 D-5 installation considerations 1-5 installing multiple MVME510x boards 1-7 MVME510x 1-16 MVME510x hardware 1-8 MVME510x into chassis 1-16 PCI mezzanine cards 1-10 PMCs 1-10 PMCspan 1-12, 1-14 primary PMCspan 1-12 secondary PMCspan 1-14 Internal Clock Frequency 4-1 interrupt from ABORT swit
Index P1 and P2 1-6 P2 Input/Output (I/O) Mod 4-7 Pal Programming Header 5-1 parallel port 6-11 parity 2-3 PC100 ECC 4-2 PC16550 2-3 PCI bus 6-5, 6-9 PCI Expansion Connector 4-2 PCI Expansion Interface 5-1 PCI expansion slot arbiter 6-7 PCI Host Bridge 4-2 PCI throughput 4-1 PCI/PMC/Expansion 4-2 Peripheral Support 4-2 PHB/SMC of Hawk ASIC 6-2 PIB controller 6-6 pin assignments IPMC761 (J3) 5-3 pinouts J1/P1, RAM500 D-7 PMC slot 1 arbiter 6-6 slot 2 arbiter 6-7 PMC Carrier Board Placement on MVME510x 1-15
PPC6-Bug> 3-2, 3-26 PPC6-Diag> 3-2, 3-26 PPCBug as initialization firmware 2-4 basics 3-1 commands 3-3 location/size requirements 3-3 overview 3-1 prompt 3-2 PPCBug commands uses of 3-1 primary PMCspan installing 1-12 Primary SCSI Bus Negotiations 3-10 Primary SCSI Data Bus Width 3-11 Processor 4-5 product specifications 4-1 programming the MVME510x 6-1 prompt, debugger 3-26 prompts PPCBug 3-2 R RAM500 bottom side connector D-7 connectors D-2, D-7 described D-2 expansion module D-1 features D-1 install ins
Index T temperature operating A-1 storage A-1 terminal setup 1-17 testing the hardware 3-26 thermal analysis E-1 thermally significant components E-2, E-3 timeout, global 1-7 timers 4-8 transition modules compatible with MVME5100 4-3 troubleshooting procedures B-1 troubleshooting the MVME510x 3-26 Tundra Universe Controller 4-2 Typical Single-width PMC Module Placement on MVME510x 1-11 U Universe VMEbus interface ASIC 2-2, 6-5, 6-6, 6-12, 6-14 uppercase 3-27 using the front panels 2-1 V VMEbus 4-2 memory
