User's Manual

6 Modifying the Environment

PrPMC800/800ET Processor PMC Module Installation and Use (PrPMC800A/IH5)

ROM First Access Length (0 - 31) = 10?

This is the value programmed into the “ROMFAL” field (Memory Control

Configuration Register 8: bits 23-27) to indicate the number of clock cycles

used in accessing the ROM. The lowest allowable ROMFAL setting is $00; the

highest allowable is $1F. The value to enter depends on processor speed; refer

to Chapter 1 or Appendix B for appropriate values. The default value varies

according to the system’s bus clock speed.

Note

ROM First Access Length is not applicable to the PrPMC800/800ET. The

configured value is ignored by PPCBug.

ROM Next Access Length (0 - 15) = 0?

The value programmed into the “ROMNAL” field (Memory Control

Configuration Register 8: bits 28-31) to represent wait states in access time for

nibble (or burst) mode ROM accesses. The lowest allowable ROMNAL setting

is $0; the highest allowable is $F. The value to enter depends on processor

speed; refer to Chapter 1, Preparation and Installation or Appendix B, Thermal

Validation for appropriate values. The default value varies according to the

system’s bus clock speed.

Note

ROM Next Access Length is not applicable to the PrPMC800/800ET. The

configured value is ignored by PPCBug.

DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?

Note

This parameter (above) also applies to enabling ECC for DRAM.

L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?

PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?

Initializes the PIRQx (PCI Interrupts) route control registers in the IBC (PCI/ISA

bus bridge controller). The ENV parameter is a 32-bit value that is divided by 4

to yield the values for route control registers PIRQ0/1/2/3. The default is

determined by system type.

Note

LED/Serial Startup Diagnostic Codes: these codes can be displayed at key

points in the initialization of the hardware devices. Should the debugger fail

to come up to a prompt, the last code displayed will indicate how far the

initialization sequence had progressed before stalling. Due to limitations

O DRAM parity is enabled upon detection. (Default)

A DRAM parity is always enabled.

N DRAM parity is never enabled.

O L2 Cache parity is enabled upon detection. (Default)

A L2 Cache parity is always enabled.

N L2 Cache parity is never enabled.