Personal Computer User Manual

3-16 Computer Group Literature Center Web Site
PPCBug Firmware
3
ROM Bank B Access Speed (ns) = 70?
This defines the minimum access speed for the Bank B Flash
Device(s) in nanoseconds.
DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?
Note This parameter also applies to enabling ECC for DRAM.
L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?
PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?
Initializes the PIRQx (PCI Interrupts) route control registers in the IBC
(PCI/ISA bus bridge controller). The ENV parameter is a 32-bit value that
is divided by 4 fields to specify the values for route control registers
PIRQ0/1/2/3. The default is determined by system type as shown:
PIRQ0=0A, PIRQ1=0B, PIRQ2=0E, PIRQ3=0F.
LED/Serial Startup Diagnostic Codes
These codes can be displayed at key points in the initialization of the
hardware devices. The codes are enabled by an ENV parameter.
Serial Startup Code Master Enable [Y/N]=N?
Should the debugger fail to come up to a prompt, the last code displayed
will indicate how far the initialization sequence had progressed before
stalling.
O DRAM parity is enabled upon detection. (Default)
A DRAM parity is always enabled.
N DRAM parity is never enabled.
O L2 Cache parity is enabled upon detection. (Default)
A L2 Cache parity is always enabled.
N L2 Cache parity is never enabled.