- Texas Instruments Floating Point Digital Signal Processor Specification Sheet


   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE
/SDCAS/SSADS
†
AOE
/SDRAS/SSOE
†
AWE
/SDWE/SSWE
†
BE1 BE2 BE3 BE4
EA
Q1 Q2 Q3 Q4
9
1
4
5
8
8
9
6
7
3
1
2
†
ARE
/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 29. SBSRAM Read Timing
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE
/SDCAS/SSADS
†
AOE/SDRAS/SSOE
†
AWE/SDWE/SSWE
†
BE1 BE2 BE3 BE4
Q1 Q2 Q3 Q4
12
11
3
1
8
12
10
4
2
1
8
5
EA
†
ARE
/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 30. SBSRAM Write Timing