- Texas Instruments Floating Point Digital Signal Processor Specification Sheet

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles
†
(see Figure 31)
NO.
GDPA-167
ZDPA−167
−200
−250
UNIT
MIN MAX
6 t
su(EDV-EKOH)
Setup time, read EDx valid before ECLKOUT high 1.5 ns
7 t
h(EKOH-EDV)
Hold time, read EDx valid after ECLKOUT high 2.5 ns
†
The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random
bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous DRAM
cycles
†‡
(see Figure 31−Figure 37)
NO. PARAMETER
GDPA-167
ZDPA−167
−200
−250
UNIT
MIN MAX
1 t
d(EKOH-CEV)
Delay time, ECLKOUT high to CEx valid 1.5 7 ns
2 t
d(EKOH-BEV)
Delay time, ECLKOUT high to BEx valid 7 ns
3 t
d(EKOH-BEIV)
Delay time, ECLKOUT high to BEx invalid 1.5 ns
4 t
d(EKOH-EAV)
Delay time, ECLKOUT high to EAx valid 7 ns
5 t
d(EKOH-EAIV)
Delay time, ECLKOUT high to EAx invalid 1.5 ns
8 t
d(EKOH-CASV)
Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.5 7 ns
9 t
d(EKOH-EDV)
Delay time, ECLKOUT high to EDx valid 7 ns
10 t
d(EKOH-EDIV)
Delay time, ECLKOUT high to EDx invalid 1.5 ns
11 t
d(EKOH-WEV)
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.5 7 ns
12 t
d(EKOH-RAS)
Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.5 7 ns
†
The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random
bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡
ARE
/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.