- Texas Instruments Floating Point Digital Signal Processor Specification Sheet

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
84
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING
timing requirements for reset
†‡
(see Figure 40)
NO.
GDPA-167
ZDPA−167
−200
−250
UNIT
MIN MAX
1 t
w(RST)
Pulse duration, RESET 100 ns
13 t
su(HD)
Setup time, HD boot configuration bits valid before RESET high
§
2P ns
14 t
h(HD)
Hold time, HD boot configuration bits valid after RESET high
§
2P ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡
The PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed to change the PLL mode in
software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Software-Programmable Phase-Lock Loop (PLL)
Controller Reference Guide (literature number SPRU233).
§
The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits
consist of: HD[8, 4:3].
switching characteristics over recommended operating conditions during reset
¶
(see Figure 40)
NO. PARAMETER
GDPA-167
ZDPA−167
−200
−250
UNIT
MIN MAX
2 t
d(RSTH-ZV)
Delay time, external RESET high to internal reset
high and all signal groups valid
#||
CLKMODE0 = 1
512 x CLKIN
period
ns
3 t
d(RSTL-ECKOL)
Delay time, RESET low to ECLKOUT high impedance 0 ns
4 t
d(RSTH-ECKOV)
Delay time, RESET high to ECLKOUT valid 6P ns
5 t
d(RSTL-CKO2IV)
Delay time, RESET low to CLKOUT2 high impedance 0 ns
6 t
d(RSTH-CKO2V)
Delay time, RESET high to CLKOUT2 valid 6P ns
7 t
d(RSTL-CKO3L)
Delay time, RESET low to CLKOUT3 low 0 ns
8 t
d(RSTH-CKO3V)
Delay time, RESET high to CLKOUT3 valid 6P ns
9 t
d(RSTL-EMIFZHZ)
Delay time, RESET low to EMIF Z group high impedance
||
0 ns
10 t
d(RSTL-EMIFLIV)
Delay time, RESET low to EMIF low group (BUSREQ) invalid
||
0 ns
11 t
d(RSTL-Z1HZ)
Delay time, RESET low to Z group 1 high impedance
||
0 ns
12 t
d(RSTL-Z2HZ)
Delay time, RESET low to Z group 2 high impedance
||
0 ns
¶
P = 1/CPU clock frequency in ns.
Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For
example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while
internal reset is asserted.
#
The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET
is deasserted, the actual delay time may vary.
||
EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0]
, BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and
HOLDA
EMIF low group consists of: BUSREQ
Z group 1 consists of: CLKR0, CLKR1, CLKX0, CLKX1, FSR0, FSR1, FSX0, FSX1, DX0, DX1, TOUT0, and TOUT1.
Z group 2 consists of: All other HPI and GPIO signals