- Texas Instruments Floating Point Digital Signal Processor Specification Sheet


   
SPRS292 − OCTOBER 2005
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st halfword 2nd halfword
5
17
86
5
17
85
15
916
15
97
4
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE
†
HCS
HD[15:0] (output)
HRDY
(case 1)
HRDY
(case 2)
3
†
HSTROBE
refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 42. HPI Read Timing (HAS Not Used, Tied High)
HAS
†
HCNTL[1:0]
HR/W
HHWIL
HSTROBE
‡
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY
(case 2)
1st half-word 2nd half-word
5178
51785
15
916
15
97
4
3
11
10
11
10
11
10
11
10
11
1011
10
19
19
18
18
†
For correct operation, strobe the HAS
signal only once per HSTROBE active cycle.
‡
HSTROBE
refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 43. HPI Read Timing (HAS Used)