- Texas Instruments Floating Point Digital Signal Processor Specification Sheet

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   
SPRS292 − OCTOBER 2005
97
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR
5
Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1
†‡
(see Figure 50)
NO.
GDPA-167
ZDPA−167
−200
−250
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 t
su(DRV-CKXH)
Setup time, DR valid before CLKX high 12 2 − 6P ns
5 t
h(CKXH-DRV)
Hold time, DR valid after CLKX high 4 5 + 12P ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.