Specifications

 iSYSTEM, February 2003 6/8
Memory Banks and Default Memory Map
The EVB-56x board provides two memory banks, which can be optionally selected by the
MPC5xx microcontroller chip selects. The memory banks are the SRAM (U6)and Simultaneous
Operation Flash EPROM (U5). Since the MPC5xx chip selects are fully programmable (with the
exception of CS0 providing external Reset start-up) the banks can be located at any location in
the MPC5xx memory space. As a reference example, iSystem has defined a default memory map
where the chip selects are located at predefined locations. The provided software uses that
memory configuration. If you modify the memory map make sure that all memory banks and chip
select configuration settings are correct.
EVB-56x Memory Map
Internal Memory
Address
Range
Memory Type Description
0000 0000-
002F 7FFF
Internal Flash Memory
(FLEN must be enabled)
Internal Flash memory banks (512KB – 1MB)
002F 8000-
002F FFFF
DEC RAM and Flash Control
Registers
Burst Buffer Controller and Decompression RAM
Registers
0030 0000-
003F 7FFF
Control and Status Registers Registers for internal peripheral circuits
003F 8000-
003F FFFF
SRAM 28KB RAM, 4KB Overlay
For details see the Reference manual.
External Memory
Address
Range
Memory Type Configuration
0000 0000-
0007 FFFF
8Mbit (512K x 16) Simultaneous
Operation Flash EPROM
(If FLEN = Off)
Base address = 0x400000, Port width = 16 bit,
Memory Range = 0x80000,
Wait state = 4
0040 0000-
0047 FFFF
8Mbit (512K x 16) Simultaneous
Operation Flash EPROM
(If FLEN = On)
Base address = 0x400000, Port width = 16 bit,
Memory Range = 0x80000,
Wait state = 4
0080 0000-
0087 FFFF
4Mbit (256K x 16) SRAM Base address = 0x800000, Port width = 16 bit,
Memory Range = 0x080000,
Wait state = 2
SRAM Memory
The asynchronous SRAM Memory is implemented with one 256K x 16 memory device. This
memory bank must be configured as a 16 bit wide port. It is byte accessible for read or write
operations. Asynchronous SRAM memory requires wait states.
Flash Memory
The Bank U5 contains AM29DL800 type flash device. It must be configured as a 16 bit wide
port. Read operations can have either byte either half-word access but write operation must be
half-word for proper operations. The device requires wait states when accessed. Refer to the
specific device data sheet and sample software provided for configuring the flash memory. Due to