Technical information

Flow Control
2-70 AT+i Commands Reference Manual May 31, 2008
Host -> W24 Hardware Flow Control
As an alternative to the software flow control method, which requires some software attention on
behalf of the host, W24 offers a hardware flow control mode.
This mode is selected by setting W24's FLW parameter Bit 0, using the AT+iFLW command.
Note that to set FLW Bit 0, the ~CTSH signal needs to be LOW (enabled), otherwise W24 returns
I/ERROR (063). This convention safeguards W24 from lockup, which may arise if FLW Bit 0 is
set while the ~CTSH signal is constantly HIGH.
For hardware flow control to operate properly, the ~CTS and ~RTS signals between the host and
W24 UARTS must be interconnected (see Figure 2-6).
The W24 ~CTSH and ~RTSH signals can be shorted to circumvent hardware flow control.
Under this mode, W24 assumes that the host transmission might be paused by de-asserting the
~CTS signal. The host must adhere to this convention. Most UARTs support hardware flow
control. However, if this is not the case, W24's ~CTS signal must be monitored by the host
software on a general purpose I/O.
The host can also pause W24 by de-asserting its ~CTS signal.
If a transmission error occurs during processing of a send command (EMB, SSND, TBSN,
FSND), W24 accepts all remaining characters pertaining to the current command (as specified by
the <sz> parameter) before returning the relevant I/ERROR response.
Figure 2-6: Minimum Hardware Flow Control Connections