Manual

3-12
BIOS Setup
MS-7695
Chapter 3
BIOS Setup
MS-7695
Chapter 3
OC Gene
Settng ths tem to [Enabled] allows the system to detect the maxmum FSB clock and
to overclock automatcally. If overclockng fals to run, you can try the lower FSB clock
for overclockng successfully.
AMD Turbo Core Technology
Ths technology automatcally ncreases the frequency of actve CPU cores to mprove
performance.
Adjust Turbo Core Rato
Ths tem s used to adjust turbo core rato.
IGD Engne CLK
Ths tem s used to adjust ntegrated graphcs clock.
DRAM Frequency
Ths tem s used to adjust the DRAM frequency. Settng to [Auto], the system wll detect
the DRAM Frequency automatcally.
DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect)
EEPROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the
followng “Advanced DRAM Conguraton” sub-menu to be determned by BIOS based
on the conguratons on the SPD. Selectng [Lnk] or [Unlnk] allows users to congure
the DRAM tmngs and the followng related “Advanced DRAM Conguraton” sub-menu
manually.
Advanced DRAM Conguraton
Press <Enter> to enter the sub-menu.
Command Rate
Ths settng controls the DRAM command rate.
tCL
Ths controls the CAS latency, whch determnes the tmng delay (n clock cycles)
before SDRAM starts a read command after recevng t.
tRCD
When DRAM s refreshed, both rows and columns are addressed separately. Ths
setup tem allows you to determne the tmng of the transton from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsucent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refreshng may be ncomplete and DRAM may fal
to retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
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