5th Generation Intel® Core™ Processor Family, Intel® Core™ M Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Datasheet – Volume 1 of 2 March 2015 Order No.
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Contents—Processor Contents Revision History..................................................................................................................9 1.0 Introduction................................................................................................................10 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Supported Technologies.........................................................................................11 Power Management Support.....................................................
Processor—Contents 4.2.5 Package C-States......................................................................................50 4.2.6 Package C-States and Display Resolutions.................................................... 53 4.3 Integrated Memory Controller (IMC) Power Management............................................54 4.3.1 Disabling Unused System Memory Outputs................................................... 55 4.3.2 DRAM Power Management and Initialization................................
Contents—Processor 7.5 7.6 7.7 7.8 Signal Groups.......................................................................................................85 Test Access Port (TAP) Connection.......................................................................... 87 DC Specifications................................................................................................. 87 Voltage and Current Specifications.......................................................................... 87 7.8.
Processor—Figures Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 Processor Platform Block Diagram..............................................................................11 Intel® Flex Memory Technology Operations................................................................. 22 Processor Display Architecture ..................................................................................26 DisplayPort* Overview.............................................................................................
Tables—Processor Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Terminology........................................................................................................... 13 Related Documents..................................................................................................16 Processor DIMM Support Summary By Product............................................................
Processor—Tables 52 53 54 55 56 57 Package Mechanical Attributes...................................................................................96 Package Loading Specifications..................................................................................97 Package Storage Specifications..................................................................................97 Intel® Core™ M Processor Family (LP-DDR3, Non-Interleaved).......................................
Revision History—Processor Revision History Revision 001 Description • • January 2015 • • Updated Table 21, Thermal Design Power (TDP) Specifications Updated Table 40, Processor Core Active and Idle Mode DC Voltage and Current Specifications. Note 3 is added to "Operating voltage" row and "Idle voltage" row.
Processor—Introduction 1.0 Introduction The 5th Generation Intel® Core™ processor family based on U-Processor line, Intel® Core™ M processor family, Mobile Intel® Pentium® processor family, and Mobile Intel® Celeron® processor family are 64-bit, multi-core processors built on 14-nanometer process technology. The processors are designed for a one-chip platform that includes a low-power Platform Controller Hub (PCH) die in the same package as the processor die.
Introduction—Processor Figure 1. Processor Platform Block Diagram DDR3L/LPDDR3 DDR Ch.A Digital Display Interface x 2 DDIx2 DDR Ch.B Embedded Display Port Cameras BIOS/FW Flash eDP SATA USB 2.0 USB 2.0/3.0 SPI HDA/I2S Gyro USB 2.0 I2C, UART or USB GPIO GPS USB 2.0/3.0 Ports HD Audio Codec EC SDIO Fingerprint Sensor PECI SMBUS SMBUS 2.0 Touch Screen I2C* USB 2.0 SPI PCI Express* 2.
Processor—Introduction • Intel® Device Protection Technology with Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) • PCLMULQDQ Instruction • Intel® Device Protection Technology with Intel® Secure Key • Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSXNI) • PAIR – Power Aware Interrupt Routing • SMEP – Supervisor Mode Execution Protection • SMAP – Supervisor Mode Access Protection • Enhanced Intel® Speedstep® Technology • Intel® Device Protec
Introduction—Processor 1.4 • Memory Open and Closed Loop Throttling • Memory Thermal Throttling • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS Package Support The 5th Generation Intel® Core™ processor family based on U-Processor Line, Mobile Intel® Pentium processor family, and Mobile Intel® Celeron® processor family are available in the following package: • 40 mm x 24 mm x 1.
Processor—Introduction Term Description DVI* Digital Visual Interface.
Introduction—Processor Term Description MLC Mid-Level Cache MSI Message Signaled Interrupt MSL Moisture Sensitive Labeling MSR Model Specific Registers NCTF Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality.
Processor—Introduction Term Description TCONTROL TCONTROL is a static value that is below the TCC activation temperature and used as a trigger point for fan speed control. When DTS > TCONTROL, the processor must comply to the TTV thermal profile. TDP Thermal Design Power: Thermal solution should be designed to dissipate this target power level. TDP is not the maximum power that the processor can dissipate. TLB Translation Look-aside Buffer TTV Thermal Test Vehicle.
Introduction—Processor Document Document Number / Location DDR3 SDRAM Specification http:// www.jedec.org DisplayPort* Specification http:// www.vesa.org Intel® 64 and IA-32 Architectures Software Developer's Manuals http:// www.intel.com/ products/processor/ manuals/index.htm 5th Generation Intel® Core™ Processor Family, Intel® Core™ M Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family March 2015 Datasheet – Volume 1 of 2 Order No.
Processor—Interfaces 2.0 Interfaces 2.1 System Memory Interface 2.1.1 • LPDDR3 down or DDR3L/DDR3L-RS Non-ECC Unbuffered Small Outline Dual InLine Memory Modules with a maximum of one DIMM per channel or down • LPDDR3 memory I/O Voltage of 1.2V. DDR3L/DDR3L-RS I/O Voltage of 1.35V • Two memory channels.
Interfaces—Processor Table 4. Table 5.
Processor—Interfaces Table 7. DRAM System Memory Timing Support Processor Intel® Core™ M Processor DRAM Device Transfer Rate (MT/s) tCL (tCK) tRCD (tCK) tRP (tCK) tCWL (tCK) Command Mode DDR3L/ DDR3L-RS 1333 8/9 8/9 8/9 7 1N/2N 1600 10/11 10/11 10/11 8 1N/2N LPDDR3 1333 10 12 12 7 0.5N 1600 12 15 15 8 0.
Interfaces—Processor Out-of-Order Scheduling While leveraging the Just-in-Time Scheduling and Command Overlap enhancements, the system memory controller continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency. If there are multiple requests to the same open page, these requests would be launched in a back-to-back manner to make optimum use of the open memory page.
Processor—Interfaces Figure 2.
Interfaces—Processor • • Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user’s viewing experience — Encode / transcode HD content — Playback of high definition content including Blu-ray Disc* — Superior image quality with sharper, more colorful images — Playback of Blu-ray* disc S3D content using HDMI (1.
Processor—Interfaces Vertex Fetch (VF) Stage The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*. Vertex Shader (VS) Stage The VS stage performs shading of vertices output by the VF function. The VS unit produces an output vertex reference for every input vertex reference received from the VF unit, in the order received. Geometry Shader (GS) Stage The GS stage receives inputs from the VS stage.
Interfaces—Processor Logical 128-Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The 128-bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations.
Processor—Interfaces The processor supports streaming any 3 independent and simultaneous display combination of DisplayPort*/HDMI*/eDP*/ monitors. In the case of 3 simultaneous displays, two High Definition Audio streams over the digital display interfaces are supported. • Each digital port is capable of driving resolutions up to 3840x2160 at 60 Hz using 4 lanes at link data rate HBR2 through DisplayPort* and 4096x2304 at 24 Hz using HDMI*.
Interfaces—Processor A DisplayPort* consists of a Main Link, Auxiliary channel, and a Hot-Plug Detect signal. The Main Link is a unidirectional, high-bandwidth, and low latency channel used for transport of isochronous data streams such as uncompressed video and audio. The Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link management and device control. The Hot-Plug Detect (HPD) signal serves as an interrupt request for the sink device.
Processor—Interfaces Figure 5. HDMI* Overview HDMI Sink HDMI Source HDMI Tx HDMI Rx TMDS Data Channel 0 TMDS Data Channel 1 TMDS Data Channel 2 TMDS Clock Channel Hot-Plug Detect Display Data Channel (DDC) CEC Line (optional) embedded DisplayPort* The embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs.
Interfaces—Processor The processor will continue to support Silent stream. Silent stream is an integrated audio feature that enables short audio streams, such as system events to be heard over the HDMI and DisplayPort monitors. The processor supports silent streams over the HDMI and DisplayPort interfaces at 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz sampling rates.
Processor—Interfaces Table 10.
Interfaces—Processor Table 12.
Processor—Interfaces Figure 6. PECI Host-Clients Connection Example VTT VTT Q3 nX Q1 nX PECI Q2 1X CPECI <10pF/Node Host / Originator PECI Client Additional PECI Clients 5th Generation Intel® Core™ Processor Family, Intel® Core™ M Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Datasheet – Volume 1 of 2 March 2015 32 Order No.
Technologies—Processor 3.0 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/technology/ 3.
Processor—Technologies • More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts. • More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.
Technologies—Processor • Descriptor-Table Exiting — Descriptor-table exiting allows a VMM to protect a guest operating system from an internal (malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table), LDT (local descriptor table), and TSS (task segment selector).
Processor—Technologies Figure 7.
Technologies—Processor • Memory controller and processor graphics comply with the Intel VT-d 1.
Processor—Technologies Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute. These extensions enhance two areas: • The launching of the Measured Launched Environment (MLE). • The protection of the MLE from potential corruption. The enhanced platform provides these launch and control interfaces using Safer Mode Extensions (SMX).
Technologies—Processor 3.4 Intel® Turbo Boost Technology 2.0 The Intel Turbo Boost Technology 2.0 allows the processor core to opportunistically and automatically run faster than its rated operating frequency/render clock, if it is operating below power, temperature, and current limits. The Intel Turbo Boost Technology 2.0 feature is designed to increase performance of both multi-threaded and single-threaded workloads. Compared with previous generation products, Intel Turbo Boost Technology 2.
Processor—Technologies cryptographic applications, such as applications that perform bulk encryption/ decryption, authentication, random number generation, and authenticated encryption. AES is broadly accepted as the standard for both government and industry applications, and is widely deployed in various protocols. Intel AES-NI consists of six Intel SSE instructions. Four instructions, AESENC, AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and decryption.
Technologies—Processor • Provides extensions to scale processor addressability for both the logical and physical destination modes • Adds new features to enhance performance of interrupt delivery • Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following: • • • Support for two modes of operation to provide backward compatibility and extensibility for future platform innovation
Processor—Technologies 3.8 Power Aware Interrupt Routing (PAIR) The processor includes enhanced power-performance technology that routes interrupts to threads or cores based on their sleep states. As an example, for energy savings, it routes the interrupt to the active cores without waking the deep idle cores. For performance, it routes the interrupt to the idle (C1) cores without interrupting the already heavily loaded cores.
Technologies—Processor 3.12 Supervisor Mode Access Protection (SMAP) Supervisor Mode Access Protection provides the next level of system protection by blocking a malicious user from tricking the operating system into branching off user data. This technology shuts down very popular attack vectors against operating systems . For more information, refer to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. 3.
Processor—Power Management 4.0 Power Management This chapter provides information on the following power management topics: Figure 8.
Power Management—Processor Figure 9.
Processor—Power Management State Description C7 Execution cores in this state behave similarly to the C6 state. If all execution cores request C7 state, L3 cache ways are flushed until it is cleared. If the entire L3 cache is flushed, voltage will be removed from the L3 cache. Power removal to SA, Cores and L3 will reduce power consumption. C8 C7 state plus voltage is removed from all power domains after required state is saved. PLL is powered down.
Power Management—Processor 4.2.2 • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores. — Once the voltage is established, the PLL locks on to the target frequency. — All active processor cores share the same frequency and voltage.
Processor—Power Management While individual threads can request low-power C-states, power saving actions only take place once the core C-state is resolved. Core C-states are automatically resolved by the processor. For thread and core C-states, a transition to and from C0 is required before entering any other C-state. 4.2.
Power Management—Processor Core C1/C1E State C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E state, see Package C-States on page 50.
Processor—Power Management This feature is disabled by default. BIOS must enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register. 4.2.5 Package C-States The processor supports C0, C1/C1E, C3, C6, C7, C8, C9, and C10 power states.The following is a summary of the general rules for package C-state entry.
Power Management—Processor Table 17. Coordination of Core Power States at the Package Level Package C-State Core 0 Core 1 C0 C1 C3 C6 C7 C8 C9 C10 C0 C0 C0 C0 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C11 C11 C11 C11 C3 C0 C11 C3 C3 C3 C3 C3 C3 C6 C0 C11 C3 C6 C6 C6 C6 C6 C7 C0 C11 C3 C6 C7 C7 C7 C7 C8 C0 C11 C3 C6 C7 C8 C8 C8 C9 C0 C11 C3 C6 C7 C8 C9 C9 C10 C0 C11 C3 C6 C7 C8 C9 C10 Note: 1.
Processor—Power Management • All cores are in a power state deeper than C1/C1E state; however, the package low-power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR. • All cores have requested C1 state using HLT or MWAIT(C1) and C1E autopromotion is enabled in IA32_MISC_ENABLES. No notification to the system occurs upon entry to C1/C1E state. Package C2 State Package C2 state is an internal processor state that cannot be explicitly requested by software.
Power Management—Processor Core break events are handled the same way as in package C3 or C6 state. Package C8 State The processor enters C8 states when the core with the highest state is C8. The package C8 state is similar to package C7 state; however, in addition, all internally generated voltage rails are turned off and the input VCC is reduced to 1.15 V to 1.3 V. Package C9 State The processor enters package C9 states when the core with the highest state is C9.
Processor—Power Management Table 18.
Power Management—Processor 4.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory in which it is not connected to any actual memory devices is tri-stated. The benefits of disabling unused SM signals are: • Reduced power consumption. • Reduced possible overshoot/undershoot signal quality issues seen by the processor I/O buffer receivers caused by reflections from potentially unterminated transmission lines.
Processor—Power Management waking-up all page-buffers are empty.) The LPDDR does not have a DLL. As a result, the power savings are as good as PPD/DLL-off, but will have lower exit latency and higher performance. The CKE is determined per rank, whenever it is inactive. Each rank has an idlecounter. The idle-counter starts counting as soon as the rank has no accesses, and if it expires, the rank may enter power-down while no new transactions to the rank arrives to queues.
Power Management—Processor When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh, the processor core flushes pending cycles and then enters SDRAM ranks that are not used by Intel graphics memory into self-refresh. The CKE signals remain LOW so the SDRAM devices perform self-refresh. The target behavior is to enter self-refresh for package C3 or deeper power states as long as there are no memory requests to service. The target usage is shown in the following table. Table 19.
Processor—Power Management In C3 or deeper power state, the processor internally gates VDDQ for the majority of the logic to reduce idle power while keeping all critical DDR pins such as CKE and VREF in the appropriate state. In C7 or deeper power state, the processor internally gates VccST for all non-critical state to reduce idle power. In S3 or C-state transitions, the DDR does not go through training mode and will restore the previous training information. 4.4 Graphics Power Management 4.4.
Power Management—Processor performance. The processor core control is maintained by an embedded controller. The graphics driver dynamically adjusts between P-States to maintain optimal performance, power, and thermals. The graphics driver will always try to place the graphics engine in the most energy efficient P-state. 4.4.5 Intel® Display Power Saving Technology (Intel® DPST) The Intel DPST technique achieves backlight power savings while maintaining a good visual experience.
Processor—Thermal Management 5.0 Thermal Management The thermal solution provides both component-level and system-level thermal management. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so that the processor: • Remains below the maximum junction temperature (TjMax) specification at the maximum thermal design power (TDP).
Thermal Management—Processor 5.2 Intel® Turbo Boost Technology 2.0 Power Monitoring When operating in turbo mode, the processor monitors its own power and adjusts the turbo frequencies to maintain the average power within limits over a thermally significant time period. The processor calculates the package power that consists of the processor core power and graphics core power.
Processor—Thermal Management Figure 12. Package Power Control 5.3.2 Turbo Time Parameter Turbo Time Parameter is a mathematical parameter (units in seconds) that controls the Intel Turbo Boost Technology 2.0 algorithm using moving average of energy usage. During a maximum power turbo event of about 1.25 x TDP, the processor could sustain PL2 for up to approximately 1.5 times the Turbo Time Parameter.
Thermal Management—Processor 5.4.1 Configurable TDP Note: Configurable TDP availability may vary between the different SKUs. With cTDP, the processor is now capable of altering the maximum sustained power with an alternate IA core base frequency. Configurable TDP allows operation in situations where extra cooling is available or situations where a cooler and quieter mode of operation is desired. Configurable TDP can be enabled using Intel's DPTF driver or through HW/EC firmware.
Processor—Thermal Management Off-lining core activity is the ability to dynamically scale a workload to a limited subset of cores in conjunction with a lower turbo power limit. It is one of the main vectors available to reduce active power. However, not all processor activity is ensured to be able to shift to a subset of cores. Shifting a workload to a limited subset of cores allows other cores to remain idle and save power. Therefore, when LPM is enabled, less power is consumed at equivalent frequencies.
Thermal Management—Processor Table 21. Thermal Design Power (TDP) Specifications Segment and Package Processor IA Cores, Graphics Config. and TDP Configuration Intel® Core™ UProcessor Line BGA 1168 Intel® Core™ UProcessor Line BGA 1168 Intel® Core™ UProcessor Line BGA 1168 Intel® Core™ M Processor BGA 1234 Table 22. Dual Core GT2 15 W Dual Core GT1 15 W Dual Core GT3 28 W Dual Core GT3 15 W Dual Core GT2 4.5 W Graphics Frequency 500 MHz to 2.
Processor—Thermal Management Table 23. Idle Power Specification Symbol Parameter Min Typical Max Unit Note PPACKAGE(C6) Package power in Package C6 state — — 0.6 W 1, 2 PPACKAGE(C7) Package power in Package C7 state — — 0.4 W 1, 2 PPACKAGE(C9) Package power in Package C9 state — — 0.03 W 1, 2 PPACKAGE(C10) Package power in Package C10 state — — 0.03 W 1, 2 Notes: 1. 2. 3. 4. 5.6 Package power includes both components in the processor package: processor and PCH.
Thermal Management—Processor 5.6.1.1 Thermal Control Circuit (TCC) Activation Offset TCC Activation Offset can be used to activate the Adaptive Thermal Monitor at temperatures lower than TjMAX. It is the preferred thermal protection mechanism for Intel Turbo Boost Technology 2.0 operation since ACPI passive throttling states will pull the processor out of turbo mode operation when triggered. An offset (in degrees Celsius) can be written to the TEMPERATURE_TARGET (0x1A2) MSR, bits [29:24].
Processor—Thermal Management times are independent of processor frequency. A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired, the Adaptive Thermal Monitor goes inactive and clock modulation ceases.
Thermal Management—Processor 5.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy) The DTS is expected to work within ±5° C over the operating range. 5.6.2.2 Fan Speed Control with Digital Thermal Sensor Digital Thermal Sensor based fan speed control (TFAN) is a recommended feature to achieve optimal thermal performance. At the TFAN temperature, Intel recommends full cooling capability well before the DTS reading reaches TjMAX. 5.6.
Processor—Thermal Management PROCHOT# only as a backup in case of system cooling failure. Overall, the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. 5.6.3.
Thermal Management—Processor Mode may be used in conjunction with the Adaptive Thermal Monitor. However, if the system software tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. If the I/O-based and MSR-based On-Demand modes are in conflict, the duty cycle selected by the I/O emulation-based On-Demand mode will take precedence over the MSR-based On-Demand Mode. 5.6.4.
Processor—Signal Description 6.0 Signal Description This chapter describes the processor signals. The signals are arranged in functional groups according to the associated interface or category. The following notations are used to describe the signal type. Signal Type Notation I Input pin O Output pin I/O Bi-directional Input/Output pin The signal description also includes the type of buffer used for the particular signal (see the following table). Table 24.
Signal Description—Processor Signal Name Table 26. Description Direction / Buffer Type SA_RAS#, SB_RAS# RAS: These signals are used with CAS# and WE# to define the command being entered. O SA_CAS#, SB_CAS# CAS: These signals are used with RAS# and WE# to define the command being entered. O SA_DQS[7:0]/ SA_DQS#[7:0] SB_DQS[7:0]/ SB_DQS#[7:0] Data Strobes: DQS and its complement DQS# signal make up a differential strobe pair.
Processor—Signal Description 6.2 Memory Compensation and Miscellaneous Signals Table 27. LPDDR3 / DDR3L / DDR3L-RS Reference and Compensation Signals Signal Name Description SM_RCOMP[2:0] System Memory Impedance Compensation: SM_PG_CNTL1 System Memory Power Gate Control: This signal disables the platform memory VTT regulator in C8 and deeper and S3 states. 6.3 Reset and Miscellaneous Signals Table 28.
Signal Description—Processor 6.4 embedded DisplayPort* (eDP*) Signals Table 29.
Processor—Signal Description Signal Name Description Direction / Buffer Type PROC_TDI Processor Test Data In: This signal transfers serial test data into the processor. This signal provides the serial input needed for JTAG specification support. PROC_TDO Processor Test Data Out: This signal transfers serial test data out of the processor. This signal provides the serial output needed for JTAG specification support.
Signal Description—Processor 6.8 Power Sequencing Signals Table 33. Power Sequencing Signals Signal Name Description Direction / Buffer Type PROCPWRGD The processor requires this input signal to be a clean indication that the VCC and VDDQ power supplies are stable and within specifications. This requirement applies regardless of the S-state of the processor.
Processor—Signal Description 6.10 Sense Signals Table 35. Sense Signals Signal Name VCC_SENSE VSS_SENSE Description Direction / Buffer Type VCC_SENSE and VSS_SENSE provide an isolated, lowimpedance connection to the processor input VCC voltage and ground. The signals can be used to sense or measure voltage near the silicon. O A 6.11 Ground and Non-Critical to Function (NCTF) Signals Table 36.
Signal Description—Processor 6.12 Processor Internal Pull-Up / Pull-Down Terminations Table 37.
Processor—Electrical Specifications 7.0 Electrical Specifications This chapter provides the processor electrical specifications including integrated voltage regulator (VR), VCC Voltage Identification (VID), reserved and unused signals, signal groups, Test Access Points (TAP), and DC specifications. 7.1 Integrated Voltage Regulator A feature to the processor is the integration of platform voltage regulators into the processor.
Electrical Specifications—Processor Table 38. Voltage Regulator (VR) 12.5 Voltage Identification B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 VCC B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex VCC 0.0000 0 0 1 0 0 0 0 1 21h 0.8200 01h 0.5000 0 0 1 0 0 0 1 0 22h 0.8300 02h 0.5100 0 0 1 0 0 0 1 1 23h 0.
Processor—Electrical Specifications B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex 0 1 0 0 0 0 1 0 42h 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 VCC B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex VCC 1.1500 0 1 1 0 0 1 0 0 64h 1.4900 43h 1.1600 0 1 1 0 0 1 0 1 65h 1.5000 0 44h 1.1700 0 1 1 0 0 1 1 0 66h 1.5100 0 1 45h 1.
Electrical Specifications—Processor B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex 1 0 0 0 0 1 1 0 86h 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 1 0 1 VCC B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex VCC 1.8300 1 0 1 0 1 0 0 0 A8h 2.1700 87h 1.8400 1 0 1 0 1 0 0 1 A9h 2.1800 0 88h 1.8500 1 0 1 0 1 0 1 0 AAh 2.1900 0 1 89h 1.
Processor—Electrical Specifications B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex 1 1 0 0 1 0 1 0 CAh 1 1 0 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 1 1 1 VCC B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex VCC 2.5100 1 1 1 0 1 1 0 0 ECh 2.8500 CBh 2.5200 1 1 1 0 1 1 0 1 EDh 2.8600 0 CCh 2.5300 1 1 1 0 1 1 1 0 EEh 2.8700 0 1 CDh 2.
Electrical Specifications—Processor 7.4 Reserved or Unused Signals The following are the general types of reserved (RSVD) signals and connection guidelines: • RSVD – these signals should not be connected • RSVD_TP – these signals should be routed to a test point Arbitrary connection of these signals to VCC, VDDQ, VSS, or to any other signal (including each other) may result in component malfunction or incompatibility with future processors.
Processor—Electrical Specifications Signal Group Type Signals Single ended DDR3L/DDR3L-RS/ LPDDR3 Bidirectional SA_DQ[63:0], SB_DQ[63:0] Differential DDR3L/DDR3L-RS/ LPDDR3 Bidirectional SA_DQSP[7:0], SA_DQSN[7:0], SB_DQSP[7:0], SB_DQSN[7:0] Reference Voltage Signals Voltage DDR3L/DDR3L-RS/ LPDDR3 Output SM_VREF_CA, SM_VREF_DQ0, SM_VREF_DQ1 Testability (ITP/XDP) Single ended GTL Input PROC_TCK, PROC_TDI, PROC_TMS, PROC_TRST# Single ended GTL PROC_TDO Single ended GTL BPM#[7:0] Single e
Electrical Specifications—Processor Signal Group Type Signals Digital Display Interface Differential DDI Output DDIB_TXP[3:0], DDIB_TXN[3:0], DDIC_TXP[3:0], DDIC_TXN[3:0]] Notes: 1. See Signal Description on page 72 for signal description details. 2. SA and SB refer to DDR3L / DDR3L-RS / LPDDR3 Channel A and DDR3L / DDR3L-RS / LPDDR3 Channel B. 7.
Processor—Electrical Specifications Symbol ICCMAX TOLVCC Parameter Segment Typ Max Voltage Range for Processor Idle Mode (Package C7 Plus) All 1.3 — — Voltage Range for Processor Idle Mode (Package C8) All 1.
Electrical Specifications—Processor Table 41. Memory Controller (VDDQ) Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note VDDQ (DDR3L/DDR3L-RS) Processor I/O supply voltage for DDR3L/DDR3LRS — 1.35 — V 2, 3 VDDQ (LPDDR3) Processor I/O supply voltage for LPDDR3 — 1.20 — V 2, 3 TOLDDQ VDDQ Tolerance (AC+DC) -5 — 5 % 2, 3 IccMAX_VDDQ (DDR3L/ Max Current for VDDQ Rail (DDR3L/DDR3L-RS) — — 1.4 A 1 — — 1.
Processor—Electrical Specifications Parameter Min Typ Max Units Notes1 RON_UP(CK) DDR3L/DDR3L-RS Clock Buffer pull-up Resistance 20 26 32 Ω 5, 11, 13 RON_DN(CK) DDR3L/DDR3L-RS Clock Buffer pull-down Resistance 20 26 32 Ω 5, 11, 13 RON_UP(CMD) DDR3L/DDR3L-RS Command Buffer pullup Resistance 15 20 25 Ω 5, 11, 13 RON_DN(CMD) DDR3L/DDR3L-RS Command Buffer pulldown Resistance 15 20 25 Ω 5, 11, 13 RON_UP(CTL) DDR3L/DDR3L-RS Control Buffer pull-up Resistance 19 25 31 Ω 5, 1
Electrical Specifications—Processor Symbol Parameter Min Typ Max Units Notes1 SM_RCOMP1 Data COMP Resistance 118.8 120 121.2 Ω 8 SM_RCOMP2 ODT COMP Resistance 99 100 101 Ω 8 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3.
Processor—Electrical Specifications Symbol Parameter Min Typ. Max Unit Note RON_DN(CMD) LPDDR3 Command Buffer pull-down Resistance 19 25 31 Ω 5, 12 RON_UP(CTL) LPDDR3 Control Buffer pull-up Resistance 19 25 31 Ω 5, 12 RON_DN(CTL) LPDDR3 Control Buffer pull-down Resistance 19 25 31 Ω 5, 12 RON_UP(RST) LPDDR3 Reset Buffer pullup Resistance 40 80 130 Ω — RON_DN(RST) LPDDR3 Reset Buffer pullup Resistance 40 80 130 Ω — ILI Input Leakage Current (DQ, CK) 0V 0.2* VDDQ 0.
Electrical Specifications—Processor Table 45. Digital Display Interface Group DC Specifications Symbol Table 46. Parameter Min Typ Max Units VIL HPD Input Low Voltage — — 0.8 V VIH HPD Input High Voltage 2.25 — 3.6 V Vaux(Tx) Aux peak-to-peak voltage at transmitting device 0.39 — 1.38 Vaux(Rx) Aux peak-to-peak voltage at receiving device 0.32 — 1.
Processor—Electrical Specifications Symbol Parameter Units Notes1 Input High Voltage (PROC_TCK, PROC_TRST#) VccST * 0.7 — V 2, 4 VHYSTERESIS Hysteresis Voltage VccST* 0.2 — V — RON Buffer on Resistance (TDO) 7 17 Ω — VIL Input Low Voltage (other GTL) — VccST* 0.6 V 2 VIH Input High Voltage (other GTL) VccST* 0.
Electrical Specifications—Processor Symbol Definition and Conditions Min Max Units Notes1 Vn Negative-Edge Threshold Voltage 0.275 * VccST 0.525 * VccST V — Vp Positive-Edge Threshold Voltage 0.550 * VccST 0.725 * VccST V — Cbus Bus Capacitance per Node N/A 10 pF — Cpad Pad Capacitance 0.7 1.8 pF — Ileak000 leakage current at 0 V — 0.6 mA — Ileak025 leakage current at 0.25* VccST — 0.4 mA — Ileak050 leakage current at 0.50* VccST — 0.
Processor—Package Specifications 8.0 Package Specifications 8.1 Package Mechanical Attributes The processors use a Flip Chip technology and Multi-Chip package (MCP) available in a Ball Grid Array (BGA) package. The following table provides an overview of the mechanical attributes of this package. Table 52.
Package Specifications—Processor 8.2 Package Loading Specifications Table 53. Package Loading Specifications Maximum Static Normal Load Limit Notes U-Processor Line 67 N (15 lbf) 1, 2, 3 Intel® Core™ M Processor Family 44 N (10 lbf) 1, 2, 3 Notes: 1. The thermal solution attach mechanism must not induce continuous stress to the package. It may only apply a uniform load to the die to maintain a thermal interface. 2.
Processor—Processor Ball and Signal Information 9.0 Processor Ball and Signal Information This chapter provides the processor Ball information. 9.1 Intel® Core™ M Processor Family Ball Information (BGA1234) This section contains ball information for the Intel® Core™ M processor family. Table 55.
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # DDPB_CTRLCLK BP43 SA_CAA8 CG10 NOT USED AR6 DDPB_CTRLDATA BN42 SA_CAB5 CF5 NOT USED AT5 DDPC_CTRLCLK BP41 NOT USED CE10 SB_CAA0 AT3 DDPC_CTRLDATA BR40 NOT USED CG8 SB_CAA2 BA8 SM_PG_CNTL1 BL14 SA_CAA0 CG6 SB_CAA4 AY3 SM_RCOMP0 CV7 SA_CAA2 CH3 SB_CAA3 AW2 SM_RCOMP1 CP7 SA_CAA4 CE6 SB_CAA1 AY5 SM_RCOMP2 CT7 SA_CAA3 CB9 SB_OD
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # SA_DQ41 BR2 SB_DQ44 AE1 SA_DQ63 BM9 SA_DQ42 BN6 SB_DQ45 AG5 SB_DQ16 BE10 SA_DQ43 BN4 SB_DQ46 AD4 SB_DQ17 BC10 SA_DQ44 BR6 SB_DQ47 AE5 SB_DQ18 BE8 SA_DQ45 BR4 SA_DQ16 CT25 SB_DQ19 BC8 SA_DQ46 BM5 SA_DQ17 CP25 SB_DQ20 BF11 SA_DQ47 BM3 SA_DQ18 CN22 SB_DQ21 BC12 SB_DQ0 BK3 SA_DQ19 CP23 SB_DQ22 BE12 SB_DQ1 BK5 SA_DQ20 CN24
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # SA_DQSN4 BV3 DDPC_HPD Y29 RSVD CJ16 SA_DQSN5 BP3 EDP_HPD W29 RSVD CK31 SB_DQSN0 BH5 RSVD_TP AL32 VSS CF39 SB_DQSN1 BD5 RSVD_TP AL34 P29 SB_DQSN4 AK2 N7 SB_DQSN5 AF2 HDA_DOCK_RST# / I2S1_SFRM UART1_RXD / GPIO0 H38 SA_DQSN2 CR24 HDA_DOCK_EN# / I2S1_TXD N5 UART1_TXD / GPIO1 GPIO10 B17 SA_DQSN3 CR20 DPWROK J7 K21 SA_DQSN6 BV9 SM
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # SML0ALERT# / GPIO60 F21 GSPI0_MISO / GPIO85 L36 SUS_STAT# / GPIO61 D25 GSPI0_MOSI / GPIO86 K33 SUSCLK / GPIO62 B27 L34 SLP_S5# / GPIO63 A18 GSPI1_CS# / GPIO87 SDIO_CLK / GPIO64 N34 GSPI1_CLK / GPIO88 M31 SDIO_CMD / GPIO65 H40 GSPI1_MISO / GPIO89 F37 SDIO_D0 / GPIO66 R40 GPIO9 D17 SDIO_D1 / GPIO67 R38 GSPI_MOSI / GPIO90 H35 SDIO_D2 / GPIO6
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # RSVD CL28 RSVD AL18 PETp2 / USB3Tp4 BC42 RSVD C5 PROC_OPI_RCOMP AB6 PETp3 AY43 BPM#0 CM39 PCH_OPI_RCOMP AB4 PETp4 AV43 BPM#1 CN38 PCH_PWROK F9 PETp5_L0 AU42 BPM#2 CK36 PCH_TCK CK17 PETp5_L1 AW42 BPM#3 CM37 PCH_TDI CL20 PETp5_L2 BA40 BPM#4 CN36 PCH_TDO CL18 PETp5_L3 BB43 BPM#5 CR35 PCH_TMS CK15 RSVD AT41 BPM#6 CN34 PCH_
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # RSVD Y33 USB2n1 T9 RSVD W33 USB2n2 Y10 SPI_CLK C26 USB2n3 AB10 SPI_CS0# H27 USB2n4 W9 SPI_CS1# M27 USB2n5 V8 SPI_CS2# K27 USB2n6 V6 SPI_IO2 F27 USB2n7 Y6 SPI_IO3 J26 USB2n8 V4 SPI_MISO B23 USB2n9 Y4 SPI_MOSI D31 USB2p0 V12 SRTCRST# D6 USB2p1 V10 RSVD H15 USB2p2 Y8 I2S1_SCLK N9 USB2p3 AA9 SUSACK# D19 USB2p4 W7 SYS
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VCCACLKPLL AK35 VCC AY45 VCC CY17 VCCCLK3 AJ28 VCC BB45 VCC CY19 VCCCLK1 AK23 VCC BD45 VCC CY21 VCC1_05 AG45 VCC BF45 VCC CY23 VCC1_05 AH36 VCC BH45 VCC CY25 VCC1_05 AJ16 VCC BK45 VCC CY27 VCC1_05 AJ45 VCC BM45 VCC CY29 VCC1_05 T17 VCC BP45 VCC CY31 VCC1_05 W22 VCC BT45 VCC CY33 VCC1_05 Y22 VCC BV41 VCC CY36
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VCCTS3_3 AB36 VSS AA25 VSS AD12 RSVD AL22 VSS AA26 VSS AD14 DCPRTC V15 VSS AA28 VSS AD16 RSVD AK33 VSS AA29 VSS AD19 VCCSATAPHY N45 VSS AA3 VSS AD24 VCCSATAPHY T45 VSS AA30 VSS AD28 RSVD CL14 VSS AA32 VSS AD32 VCCCLK7 AJ26 VSS AA33 VSS AD44 VCCCLK5 AL39 VSS AA34 VSS AD6 VCCST AJ20 VSS AA35 VSS AE16 VCCST_PWRG
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VSS AH20 VSS AM31 VSS AV9 VSS AH21 VSS AM35 VSS AW14 VSS AH22 VSS AM39 VSS AW44 VSS AH23 VSS AM45 VSS AY1 VSS AH25 VSS AN10 VSS AY13 VSS AH26 VSS AN12 VSS AY15 VSS AH27 VSS AN14 VSS AY39 VSS AH28 VSS AN2 VSS AY7 VSS AH29 VSS AN4 VSS BA44 VSS AH30 VSS AN40 VSS BB11 VSS AH31 VSS AN42 VSS BB13 VSS AH32 V
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VSS BH39 VSS BU40 VSS CD15 VSS BH41 VSS BU42 VSS CD3 VSS BH43 VSS BU44 VSS CD39 VSS BH7 VSS BV13 VSS CD5 VSS BJ44 VSS BV15 VSS CD7 VSS BK13 VSS BV39 VSS CD9 VSS BK15 VSS BV7 VSS CE14 VSS BK39 VSS BW14 VSS CE44 VSS BK7 VSS BY1 VSS CF13 VSS BL10 VSS BY11 VSS CF15 VSS BL12 VSS BY13 VSS CF7 VSS BL2 VSS B
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VSS CM19 VSS CV41 VSS H42 VSS CM21 VSS CW12 VSS J1 VSS CM23 VSS CW14 VSS J16 VSS CM25 VSS CW16 VSS J20 VSS CM31 VSS CW18 VSS J24 VSS CM35 VSS CW20 VSS J28 VSS CM43 VSS CW22 VSS J3 VSS CN1 VSS CW24 VSS J32 VSS CN26 VSS CW26 VSS J43 VSS CN42 VSS CW28 VSS J45 VSS CN5 VSS CW30 VSS L16 VSS CN8 VSS CW32 V
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VSS R6 VSS Y32 VSS R8 VSS Y40 VSS T13 VSS Y42 VSS T15 VSS Y44 VSS T19 VSS CA14 VSS T23 VSS AM33 VSS T29 VSS AJ13 VSS U14 VSS_SENSE CH43 VSS U20 WAKE# F19 VSS U22 RSVD BK41 VSS U24 RSVD BK43 VSS U26 DIFFCLK_BIASREF A38 VSS U28 XTAL24_IN AR44 VSS U32 XTAL24_OUT AP45 VSS U34 VSS V17 VSS V2 VSS V40 VSS V44 VSS W16 VSS W18 VSS W19 V
Processor Ball and Signal Information—Processor 9.2 U-Processor Ball Information (BGA1168) This section contains ball information for the 5th Generation Intel® Core™ processor family based on U-Processor Line, Mobile Intel® Pentium® processor family, and Mobile Intel® Celeron® processor family. Table 56.
Processor—Processor Ball and Signal Information Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # DCPRTC AE7 DEVSLP1 / GPIO38 L2 GPIO47 AB6 DCPSUS1 AD10 DEVSLP2 / GPIO39 N5 GPIO48 U4 DCPSUS1 AD8 DIFFCLK_BIASREF C26 GPIO49 Y3 DCPSUS2 AH13 DPWROK AV5 GPIO50 P3 DCPSUS3 J13 DSWVRMEN AW7 GPIO51 R5 DCPSUS4 AB8 EDP_AUXN A45 GPIO52 L1 DCPSUSBYP AG19 EDP_AUXP B45 GPIO53 L4 DCPSUSBYP AG20 eDP_BKLCTL B8 GPIO54 L3 DDI1_TXN[0] C54 eDP_B
Processor Ball and Signal Information—Processor Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # PETp5_L0 C22 PETp5_L1 A23 PETp5_L2 C21 PETp5_L3 A21 PIRQA# / GPIO77 U6 PIRQB# / GPIO78 P4 N62 PIRQC# / GPIO79 N4 PERn1 / USB3Rn3 G17 PIRQD# / GPIO80 N2 AY8 PERn2 / USB3Rn4 F15 PLTRST# AG7 INTRUDER# AU6 PERn3 G11 PME# AD4 INTVRMEN AV7 PERn4 F13 PRDY# J62 JTAGX AE63 PERn5_L0 F10 PREQ# K62 LAD0 AU14 PERn5_L1 F8 PROC_DETECT# D61 LAD1
Processor—Processor Ball and Signal Information Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # RSVD V59 RSVD E1 SA_BA0 AU35 RSVD U59 RSVD D1 SA_BA1 AV35 RSVD AL1 RSVD J20 SA_BA2 AY41 RSVD AP7 RSVD H18 SA_CAS# AU34 RSVD AM11 RSVD AN10 SA_CKE0 AU43 RSVD AV62 RSVD AM10 SA_CKE1 AW43 RSVD D58 RSVD L59 SA_CKE2 AY42 RSVD P20 RSVD J58 SA_CKE3 AY43 RSVD R20 RSVD Y20 SA_CLK#0 AU37 RSVD N60 RSVD AC20 SA_CLK#1 AW36 RSVD A
Processor Ball and Signal Information—Processor Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # SA_DQ44 AV54 SA_DQ6 AK61 SA_MA5 AR36 SA_DQ45 AU54 SB_DQ44 AV19 SA_MA6 AV40 SA_DQ3 AK62 SB_DQ45 AU19 SA_MA7 AW39 SA_DQ46 AV52 SB_DQ46 AV17 SA_MA8 AY39 SA_DQ47 AU52 SB_DQ47 AU17 SA_MA9 AU40 SB_DQ0 AY31 SA_DQ7 AK60 SA_ODT0 AP32 SB_DQ1 AW31 SA_DQ8 AM63 SA_RAS# AY34 SB_DQ2 AY29 SA_DQ9 AM62 SA_WE# AW34 SB_DQ3 AW29 SA_DQSN0 AJ61 SAT
Processor—Processor Ball and Signal Information Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # SATA1GP / GPIO35 U1 SA_DQ56 AM46 SB_DQ56 AN20 SATA2GP / GPIO36 V6 SA_DQ57 AK46 SB_DQ57 AR20 SATA3GP / GPIO37 AC1 SA_DQ58 AM49 SB_DQ58 AK18 SATALED# U3 SA_DQ59 AK49 SB_DQ59 AL18 SB_BA0 AL35 SA_DQ60 AM48 SA_DQ22 AR57 SB_BA1 AM36 SA_DQ61 AK48 SB_DQ60 AK20 SB_BA2 AU49 SA_DQ19 AK57 SB_DQ61 AM20 SB_CAS# AM33 SA_DQ62 AM51 SB_DQ62 AR18 S
Processor Ball and Signal Information—Processor Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # SB_MA15 AP46 SM_VREF_DQ0 AR51 THERMTRIP# D60 SB_MA2 AP42 SM_VREF_DQ1 AP51 G1 SB_MA3 AR42 AN2 SB_MA4 AR45 SMBALERT# / GPIO11 UART0_CTS# / GPIO94 J2 SB_MA5 AP45 SMBCLK AP2 UART0_RTS# / GPIO93 AW46 AH1 UART0_RXD / GPIO91 J1 SB_MA6 SMBDATA SB_MA7 AY46 SML0ALERT# / GPIO60 AL2 UART0_TXD / GPIO92 K3 SB_MA8 AY47 SML0CLK AN1 J4 SB_MA9 AU46 SML
Processor—Processor Ball and Signal Information Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # USB3Tp2 A33 VCC F28 VCC W57 USBRBIAS AJ11 VCC F32 VCC_SENSE E63 USBRBIAS# AJ10 VCC F36 VCC1_05 P9 VCC F59 VCC F40 VCC1_05 N8 VCC AB57 VCC F44 VCC1_05 AE8 VCC AD57 VCC F48 VCC1_05 AF22 VCC AG57 VCC F52 VCC1_05 H11 VCC C24 VCC F56 VCC1_05 H15 VCC C28 VCC G23 VCC1_05 J11 VCC C32 VCC G25 VCC1_05 AG16 VCC C36 VCC G27 V
Processor Ball and Signal Information—Processor Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # VCCRTC AG10 VSS N21 VSS AG23 VCCSATA3PLL B11 VSS A11 VSS AG1 VCCSDIO U8 VSS A14 VSS AG11 VCCSDIO T9 VSS A18 VSS AG60 VCCSPI Y8 VSS A24 VSS AG61 VCCST AC22 VSS A28 VSS AG62 VCCST AE22 VSS A32 VSS AG63 VCCST AE23 VSS A36 VSS AH17 VCCST_PWRGD B59 VSS A40 VSS AH19 VCCSUS3_3 AH11 VSS A48 VSS AH20 VCCSUS3_3 AA9 VSS A52
Processor—Processor Ball and Signal Information Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # VSS AJ43 VSS AM17 VSS AP54 VSS AJ45 VSS AM23 VSS AP57 VSS AJ47 VSS AM31 VSS AR11 VSS AJ50 VSS AM52 VSS AR15 VSS AJ52 VSS AN17 VSS AR17 VSS AJ54 VSS AN23 VSS AR23 VSS AJ56 VSS AN31 VSS AR31 VSS AJ58 VSS AN32 VSS AR33 VSS AJ60 VSS AN35 VSS AR39 VSS AJ63 VSS AN36 VSS AP48 VSS AK23 VSS AN39 VSS AR49 VSS AK3 VSS A
Processor Ball and Signal Information—Processor Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # VSS AU53 VSS AW60 VSS D12 VSS AU55 VSS AY11 VSS D14 VSS AU57 VSS AY16 VSS D18 VSS AU59 VSS AY18 VSS D21 VSS AV14 VSS AY22 VSS D23 VSS D62 VSS AY24 VSS D25 VSS AV16 VSS AY26 VSS D26 VSS AV20 VSS AY30 VSS D27 VSS AV24 VSS AY33 VSS D29 VSS AV28 VSS AY51 VSS D2 VSS AV33 VSS AY53 VSS D30 VSS AV34 VSS AY57 VSS D3
Processor—Processor Ball and Signal Information Signal Name (DDR3) Ball # Signal Name (DDR3) Ball # VSS F20 VSS M22 VSS D5 VSS N10 VSS F26 VSS N3 VSS F30 VSS C57 VSS F34 VSS P59 VSS F38 VSS P63 VSS G6 VSS R10 VSS F46 VSS R8 VSS F50 VSS T1 VSS F54 VSS T58 VSS F58 VSS D8 VSS F61 VSS U20 VSS G18 VSS U22 VSS G22 VSS U61 VSS G3 VSS V10 VSS G5 VSS V3 VSS G8 VSS V7 VSS H13 VSS W20 VSS H17 VSS Y10 VSS H57 VSS U9 VSS J10 VSS Y59
Processor Ball and Signal Information—Processor Table 57.
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # DDI1_TXN[3] A57 EDP_RCOMP D20 GPIO58 AL4 DDI1_TXP[0] C55 EDP_TXN0 C45 GPIO59 AT5 DDI1_TXP[1] C58 EDP_TXN1 A47 GPIO8 AU2 DDI1_TXP[2] A55 EDP_TXN2 C47 GPIO9 AM3 DDI1_TXP[3] B57 EDP_TXN3 A49 GSPI_MOSI / GPIO90 K2 DDI2_TXN[0] C51 EDP_TXP0 B46 GSPI0_CLK / GPIO84 L6 DDI2_TXN[1] C53 EDP_TXP1 B47 R6 DDI2_TXN[2] C49 EDP_TXP2 C46 GSP
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # JTAGX AE63 PERn5_L1 F8 PROC_DETECT# D61 LAD0 AU14 PERn5_L2 H10 PROC_OPI_RCOMP AY15 LAD1 AW12 PERn5_L3 E6 PROC_TCK E60 LAD2 AY12 PERp1 / USB3Rp3 F17 PROC_TDI F63 LAD3 AW11 PERp2 / USB3Rp4 G15 PROC_TDO F62 LAN_PHY_PWR_CTRL / GPIO12 AM7 PERp3 F11 PROC_TMS E61 LFRAME# AV12 PERp4 G13 PROC_TRST# E59 OC0# / GPIO40 AL3 PERp5_L0 E10
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # RSVD AB21 RSVD AC58 SA_CS#0 AP33 RSVD AY14 RSVD AB23 SA_CS#1 AR32 RSVD AW14 RSVD AD23 SA_DQ0 AH63 RSVD E15 RSVD AA23 SA_DQ1 AH62 RSVD E13 RSVD AE59 SA_DQ10 AP63 RSVD AL11 RSVD K18 SA_DQ11 AP62 RSVD AC4 RSVD M20 SA_DQ12 AM61 RSVD A5 RSVD K21 SA_DQ13 AM60 RSVD N23 RSVD M21 SA_DQ14 AP61 RSVD T23 RSVD_TP AV63 SA_DQ
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # SATA_Rn1 / PERn6_L2 J8 SATA_Rn2 / PERn6_L1 J6 SATA_Rn3 / PERn6_L0 F5 SATA_Rp0 / PERp6_L3 H5 SATA_Rp1 / PERp6_L2 H8 SATA_Rp2 / PERp6_L1 H6 SATA_Rp3 / PERp6_L0 E5 SATA_Tn0 / PETn6_L3 B15 SATA_Tn1 / PETn6_L2 A17 SATA_Tn2 / PETn6_L1 B14 SATA_Tn3 / PETn6_L0 C17 SATA_Tp0 / PETp6_L3 A15 SATA_Tp1 / PETp6_L2 B17 SATA_Tp2 / PETp6_L1 C15 SATA_Tp3 / PE
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # SB_CK1 AL38 SB_DQ18 AL28 SA_DQ25 AR55 SB_CKE0 AY49 SB_DQ19 AK28 SA_DQSN2 AM58 SB_CKE1 AU50 SB_DQ20 AR29 SA_DQSN3 AM55 SB_CKE2 AW49 SB_DQ21 AN29 SA_DQSN6 AL43 SB_CKE3 AV50 SB_DQ22 AR28 SA_DQSN7 AL48 SB_CS#0 AM32 SB_DQ23 AP28 SB_DQSN2 AN28 SB_CS#1 AK32 SA_DQ20 AL58 SB_DQSN3 AN25 SA_DQ16 AP58 SB_DQ24 AN26 SB_DQSN6 AN21 SA_D
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # SB_CAB2 AK35 SML1DATA / GPIO74 AH3 USB2n0 AN8 SDIO_CLK / GPIO64 E3 SPI_CLK AA3 USB2n1 AR7 SDIO_CMD / GPIO65 F4 SPI_CS0# Y7 USB2n2 AR8 SDIO_D0 / GPIO66 D3 SPI_CS1# Y4 USB2n3 AR10 SDIO_D1 / GPIO67 E4 SPI_CS2# AC2 USB2n4 AM15 SDIO_D2 / GPIO68 C3 SPI_IO2 Y6 USB2n5 AM13 SDIO_D3 / GPIO69 E2 SPI_IO3 AF1 USB2n6 AP11 SDIO_POWER_EN / GP
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VCC C44 VCC G31 VCC3_3 W9 VCC C48 VCC G33 VCC3_3 K14 VCC C52 VCC G35 VCC3_3 K16 VCC C56 VCC G37 VCCACLKPLL A20 VCC E23 VCC G39 VCCAPLL AA21 VCC E25 VCC G41 VCCAPLL W21 VCC E27 VCC G43 VCCASW AE9 VCC E29 VCC G45 VCCASW AF9 VCC E31 VCC G47 VCCASW AG8 VCC E33 VCC G49 VCCASW AG13 VCC E35 VCC G51 VCCASW AG14
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VCCSUS3_3 AE20 VSS AA1 VSS AH28 VCCSUS3_3 AE21 VSS A44 VSS AH30 VCCTS1_5 J15 VSS AA58 VSS AH32 VCCUSB3PLL B18 VSS AB10 VSS AH34 VDDQ AH26 VSS AB20 VSS AH36 VDDQ AJ31 VSS AE5 VSS AH38 VDDQ AJ33 VSS AB22 VSS AH40 VDDQ AJ37 VSS AB7 VSS AH42 VDDQ AN33 VSS AC61 VSS AH44 VDDQ AP43 VSS AD3 VSS AH49 VDDQ AR48 VSS
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VSS AK52 VSS AN42 VSS AR52 VSS AL10 VSS AN43 VSS AT13 VSS AL13 VSS AN45 VSS AT35 VSS AL17 VSS AN46 VSS AT37 VSS AL20 VSS AN48 VSS AT40 VSS AL22 VSS AN49 VSS AT42 VSS AL23 VSS AN51 VSS AT43 VSS AL26 VSS AN52 VSS AT46 VSS AL29 VSS AN60 VSS AT49 VSS AL31 VSS AN63 VSS AT61 VSS AL33 VSS AN7 VSS AT62 VSS AL3
Processor Ball and Signal Information—Processor Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VSS AV36 VSS AY59 VSS D33 VSS AV39 VSS AY6 VSS D34 VSS AV41 VSS AY4 VSS D35 VSS AV43 VSS B20 VSS D37 VSS AV46 VSS B24 VSS D38 VSS AV49 VSS B26 VSS D39 VSS AV51 VSS B28 VSS D41 VSS AV55 VSS B32 VSS D42 VSS AV59 VSS C38 VSS D43 VSS AV8 VSS B36 VSS D45 VSS AW16 VSS B4 VSS D46 VSS AW24 VSS B40 VSS D47
Processor—Processor Ball and Signal Information Signal Name (LP-DDR3) Ball # Signal Name (LP-DDR3) Ball # VSS G18 VSS U22 VSS G22 VSS U61 VSS G3 VSS V10 VSS G5 VSS V3 VSS G8 VSS V7 VSS H13 VSS W20 VSS H17 VSS Y10 VSS H57 VSS U9 VSS J10 VSS Y59 VSS J22 VSS Y63 VSS J59 VSS W22 VSS J63 VSS V58 VSS K1 VSS AH46 VSS K12 VSS V23 VSS R22 VSS AH16 VSS L13 VSS_SENSE E62 VSS L15 WAKE# AJ5 VSS L17 XTAL24_IN A25 VSS L18 XTAL24_OUT B25 VSS
