DatasheetDirect.com Your dedicated source for free downloadable datasheets. Over one million datasheets Optimized search function Rapid quote option Free unlimited downloads Visit www.datasheetdirect.com to get your free datasheets. This datasheet has been downloaded by http://www.datasheetdirect.
Intel® 815E Scalable Performance Board Development Kit Manual April 2001 Order Number: 273432-003
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Contents 1 About This Manual ..................................................................................................... 7 1.1 1.2 1.3 1.4 1.5 2 Getting Started ..........................................................................................................11 2.1 2.2 2.3 2.4 2.5 2.6 3 Content Overview.................................................................................................. 7 Text Conventions ..................................................................
3.4.7 3.5 4 Hardware Reference ............................................................................................... 31 4.1 4.2 4.3 4.4 4.5 5 Thermal Management ......................................................................................... 31 Post Code Debugging ......................................................................................... 31 Connector Pinouts............................................................................................... 32 4.3.
5.4.1 5.4.2 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 Basic CMOS Configuration Screen ....................................................52 Configuring Drive Assignments ..........................................................53 5.4.2.1 Configuring Floppy Drive Types ...........................................53 5.4.3 Configuring IDE Drive Types ..............................................................54 Configuring Boot Actions.......................................................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Related Documents............................................................................................. 10 Power Connector (ATXPR1) ............................................................................... 34 USB Connector Pinout (USB1) ........................................................................... 34 PS/2-Style Mouse and Keyboard Pinout (U1).................................................... 35 VGA Connector Pinout (VGA).......
About This Manual 1 This manual tells you how to set up and use the evaluation board and processor assembly included in your Intel® 815E Scalable Performance Board Development Kit. 1.1 Content Overview Chapter 1, “About This Manual” — This chapter contains a description of conventions used in this manual. The last few sections tell you how to obtain literature and contact customer support.
About This Manual Numbers Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H. A zero prefix is added to numbers that begin with A through F. (For example, FF is shown as 0FFH.) Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity.
About This Manual 1.3 Technical Support 1.3.1 Electronic Support Systems Intel’s site on the World Wide Web (http://www.intel.com/) provides up-to-date technical information and product support. This information is available 24 hours per day, 7 days per week, providing technical information whenever you need it.Telephone Technical Support In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m. and 5 p.m. PST. You can also fax your questions to us.
About This Manual 1.5 Table 1. Related Documents Related Documents Document Title Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.
Getting Started 2 This chapter identifies the evaluation kit’s key components, features and specifications. It also tells you how to set up the board for operation. 2.1 Overview The evaluation board consists of a baseboard (with one Intel® Pentium® III processor populated), 815E chipset, and other system board components and peripheral connectors. Note: 2.1.1 The evaluation board is shipped as an open system allowing for maximum flexibility in changing hardware configuration and peripherals.
Getting Started Flash System BIOS ROM • General Software system BIOS Power Supply/Management • Standard ATX power supply connector • SMRAM space remapping to A0000H (128 Kbyte) • Optional Extended SMRAM space above 256 Mbyte, additional 512 Kbyte/1 Mbyte TSEG from top of memory, cacheable • Stop clock grant and halt special cycle translation from the host to the hub interface • APIC buffer management Accelerated Graphics Port (AGP) Support • AGP Interface Specification Rev 2.
Getting Started • • • • • 2.2 Built-in Wake On LAN (WOL) header Three built-in FAN power connectors (FAN1, FAN2 and FAN3) Power/Reset jumpers Jumper to select PSB speed (66, 100, or 133 MHz) Jumper to clear CMOS Included Hardware 2.
Getting Started 2.3.1 Embedded BIOS for the Intel® 815E Scalable Performance Board Development Kit The Intel® 815E Scalable Performance Board Development Kit ships pre-installed with Embedded BIOS* pre-boot firmware from General Software. Embedded BIOS provides an industry-standard BIOS platform to run any standard operating system, including DOS*, Windows* NT, NT Embedded*, Windows 95/98, Windows CE, QNX*, VxWorks*, and Linux* among others.
Getting Started • A selected subset of the standard Linux distribution tailored for embedded development and deployment, with LynuxWorks cross-development and embedding tools. Components are selected to ensure functionality, reliability, and maintainability, both on the host and target side. BlueCat Linux is configurable to meet varied requirements for kernel size, hardware configurations, boot method, and other embedded requirements.
Getting Started • WindNet SNMP v.1/v.2c with MIB compiler—optional • WindNet OSPF v.2—optional Fast, flexible I/O and local file system • • • • • • SCSI support MS-DOS compatible file system Raw disk file system TrueFFS flash file system—optional ISO 9660 CD-ROM file system PCMCIA support Target Development Features • Full ANSI C compliance and enhanced C++ features for exception handling and template support • • • • • • • • • • Extensive POSIX 1003.1, .
Getting Started • RAD6000 • ST 20 • TriCore 2.3.3 Information/Drivers CD ABIT, the manufacturer of the baseboard, has provided a CD that contains drivers for the standard versions of the Windows operating systems (Windows 95/98/NT/2000). The CD includes drivers for on-board audio, on-board video and Intel® ATA/66. In addition, there are a few other utilities provided that may be useful. For updated drivers, refer to: http://developer.intel.com/design/chipsets/815e/index.htm 2.
Getting Started 2.5 Setting up the Evaluation Board Once you have gathered the hardware described in section Section 2.4, follow the steps below to set up your evaluation board. This manual assumes you are familiar with the basic concepts involved with installing and configuring hardware for a personal computer system. Refer to Figure 3 on page 32 for locations of connectors, jumpers, etc.
Getting Started — Connect the other end of the cable to the hard disk drive. — Connect a power cable to the hard drive. Caution: Make sure the tracer on the ribbon cable is aligned with pin 1 on both the hard disk and the IDE connector header. Connecting the cable backwards can damage the evaluation board or the hard disk. 7. Connect any additional storage devices to the evaluation board.
Getting Started 2.6 Configuring the BIOS General Software’s BIOS is pre-loaded on the evaluation board. You will need to make changes to the BIOS to enable hard disks, floppy disks and other supported features. You can use the Setup program to modify BIOS settings and control the special features of the system. Setup options are configured through a menu-driven user interface. Chapter 5, “BIOS Quick Reference” contains a description of BIOS options.
3 Theory of Operation 3.1 Block Diagram Figure 1.
Theory of Operation 3.2 Mechanical Design The evaluation board conforms to the micro-ATX form factor. For extra protection in a development environment, you may want to install the evaluation board in an ATX chassis. The evaluation board has three 32 bit/33 MHz PCI connectors, one AGP connector, one CNR connector, three SDRAM DIMM connectors, and one ABIT V-Bus connector. The system I/O connectors are in the rear of the board in the defined micro-ATX I/O window. 3.
Theory of Operation • Support for 66 MHz, 100 MHz and 133 MHz processor system bus frequencies • Intel® processor serial number 3.4.2 Intel® Celeron™ Processor The Intel® Celeron™ processor family delivers quality, reliability, and compatibility while offering good performance for today’s most widely-used applications.
Theory of Operation • System DRAM controller — Three DIMM slots — 100/133 MHz clock • Accelerated hub architecture • Digital video out port • AGP 1X/2X/4X port 3.4.3.2 I/O Controller Hub (ICH2) The Intel 82801BA I/O Controller Hub (ICH2) is a highly integrated multifunctional I/O controller hub that provides the interface to the PCI bus and integrates many of the functions needed in today’s PC platforms. The ICH2 communicates with the host controller over a dedicated hub interface.
Theory of Operation • • • • • 3.4.4 Symmetrically-blocked flash memory array (64 Kbyte) Pin and register-based block locking Integrated hardware RNG Single-byte read/write Five GPIs System Memory SDRAM Memory Features: • Three 168-pin SDRAM DIMM sockets • Supports 8 Mbyte to 512 Mbyte using 16 Mbit/64 Mbit/128 Mbit/256 Mbit technology • Supports 100/133 MHz system memory bus 3.4.5 Boot ROM The system boot ROM installed at U23 is the Intel® FWH, N82802AC8 device.
Theory of Operation Figure 2. Back Panel I/O Connectors LPT Port Connector Mouse Game Port USB Keyboard COM1 t VGA e Lin Ou n eI Lin C MI In A8332-01 3.4.6.1 Floppy Disk Drive Support One 34-pin floppy connector is provided on the evaluation board. 3.4.6.2 IDE Support The evaluation board supports both a primary and secondary IDE interface via two 40-pin IDE connectors. IDE1 is the primary interface and IDE2 is the secondary interface. 3.4.6.
Theory of Operation 3.4.6.7 Audio Subsystem The evaluation board has an integrated (on-board) AC’97 compliant subsystem. Audio Subsystem Features: • Line input (back panel) • Line output (back panel) • Microphone input (back panel) 3.4.6.8 Game Port Connector The game port connector is a standard 15-pin DSUB connector for attaching a joystick, game pad or other MIDI device. 3.4.6.9 Keyboard/Mouse The keyboard and mouse connectors (U1) are PS/2 style, 6-pin stacked miniature DSUB connectors.
Theory of Operation 3.4.7.2 32-bit/33-MHz PCI Connectors Three industry standard 32-bit/33-MHz PCI connectors (PCI1, PCI2, and PCI3) are provided on the evaluation board. 3.4.7.3 CNR Connectors One CNR connector is included on the board. Intel® has not validated this feature. 3.4.7.4 V-Bus Connector A V-BUS TV-out adapter can be installed in this connector (VL1), which has general video output and S-Video out for display on a TV monitor. Intel has not validated this feature.
Theory of Operation 3.4.10 Power Supply Requirements The Intel® 815E Scalable Performance Board uses a standard ATX power supply. 3.5 Battery Requirements A type 2032, socketed, 3 V lithium coin cell battery is used on this evaluation board. The battery has a shelf life of greater than three years.
Hardware Reference 4 This section provides reference information on the hardware, including connector pinout information and jumper settings. 4.1 Thermal Management The development kit is shipped with a heatsink/fan thermal solution pre-installed on the processor using metal clips. This thermal solution has been tested in an open-air environment at room temperature and is sufficient for evaluation purposes.
Hardware Reference 4.3 Connector Pinouts Figure 3.
Hardware Reference Figure 4.
Hardware Reference 4.3.1 ATX Power Connector Table 2 shows the signals assigned to the ATX style power connector. Table 2. 4.3.2 Power Connector (ATXPR1) Pin Name Function 1 3.3 V 3.3 V 2 3.3 V 3.3 V 3 GND Ground 4 +5V +5 V VCC 5 GND Ground 6 +5 V +5 V VCC 7 GND Ground 8 PWRGD Power Good 9 5VSB Standby 5 V 10 +12 V +12 V 11 3.3 V 3.
Hardware Reference 4.3.3 PS/2-Style Mouse and Keyboard Connectors Table 4 shows the signals assigned to the keyboard and mouse connector (U1). The mouse port is on the top and the keyboard port is on the bottom. Table 4. PS/2-Style Mouse and Keyboard Pinout (U1) Pin 4.3.4 Table 5.
Hardware Reference 4.3.5 Parallel Port Table 6 shows the signals assigned to the parallel port connector (LPT1). Table 6. 4.3.
Hardware Reference 4.3.7 Audio Connectors Refer to Figure 2 on page 26 for the connectors referenced in this section. Table 8 shows the signals assigned to the audio line-out connector. Table 8. Audio Line-Out Connector Pinouts Pin Signal Name Sleeve GND Tip Audio Left Out Ring Audio Right Out Table 9 shows the signals assigned to the audio line-in connector. Table 9.
Hardware Reference 4.3.8 Wake On LAN (WOL) Table 12 shows the signals assigned to the Wake-ON-LAN (WOL) connector (WOL1). Table 12. Wake-ON-LAN Connector Pinouts (WOL1, not populated) 4.3.9 Pin Signal Name 1 5 VSB 2 Ground 3 WOL Front Panel I/O Connectors Table 13 shows the signals assigned to the front panel I/O connectors (PN1 and PN2). Table 13. Front Panel I/O Connectors PN1 4.3.
Hardware Reference Table 14. IDE Connector Pinouts for IDE1 and IDE2 (Sheet 2 of 2) Pin 4.3.
Hardware Reference Table 15. Floppy Drive Connector Pinouts (FDC1) (Sheet 2 of 2) Pin 4.3.12 Signal Name Pin Signal Name 29 Ground 30 Read Data# 31 Ground 32 Side 1 Select# 33 Ground 34 Diskette Change# 32-Bit PCI Slot Connector Table 16 shows the signals assigned to the 32-Bit PCI slot connectors (PCI1, PCI2, and PCI3). Table 16.
Hardware Reference Table 16. 32-Bit PCI Slot Connector Pinouts (Sheet 2 of 2) Pin A25 4.3.13 Signal Name AD24 Signal Name Pin B25 Signal Name Pin 3.3 V A56 Pin GND B56 Signal Name AD3 A26 IDSEL B26 CBE3# A57 AD2 B57 GND A27 3.3 V B27 AD23 A58 AD0 B58 AD1 A28 AD22 B28 GND A59 VCC B59 VCC A29 AD20 B29 AD21 A60 REQ64# B60 ACK64# A30 GND B30 AD19 A61 VCC B61 VCC A31 AD18 B31 3.3 V A62 VCC B62 VCC 4.5.
Hardware Reference Table 17. AGP Connector Pinouts (Sheet 2 of 2) Pin Signal Pin Signal 23 KEY KEY 56 AD9 AD10 24 KEY KEY 57 C/BE0# AD8 25 KEY KEY 58 3.3 Vddq 3.3 Vddq 26 AD30 AD31 59 Reserved AD_STB0 27 AD28 AD29 60 AD6 AD7 28 3.3 VCC 3.3 VCC 61 GND GND 29 AD26 AD27 62 AD4 AD5 30 AD24 AD25 63 AD2 AD3 31 GND GND 64 3.3 Vddq 3.3 Vddq 32 Reserved AD_STB1 65 AD0 AD1 33 C/BE3# AD23 66 Reserved Reserved NOTES: 1.
Hardware Reference 4.3.14 CNR Connector Table 18 and Table 19 shows the signals assigned to the Type A and Type B CNR connectors (CNRSLOT1). Table 18.
Hardware Reference Table 19.
Hardware Reference 4.4 Jumpers 4.4.1 PN1 and PN2 Headers These headers provide the signals to the LED, power/reset button and speaker that are usually connected to the chassis when the system is mounted in a chassis. 4.4.1.1 Power LED (PN1: Pins 1—3) An LED designed for the front panel of a chassis can be connected to these pins to show the poweron status. 4.4.1.
Hardware Reference Figure 5. PN1, PN2 Diagram 4.4.2 CMOS (JP1) JP1 controls the power to the battery backed-up CMOS memory. This CMOS memory stores system information required by the BIOS during startup. For normal operation, jumper pins 1 and 2. To clear the CMOS RAM, perform the following steps: 1. Shut down the system. 2. Disconnect the power supply (ATXPR1). 3. Remove jumper from pins 1 and 2. Short pins 2 and 3 (clear CMOS). 4. Wait 10 seconds. 5.
Hardware Reference JP5 1 2 3 4 5 2 4 6 8 10 1 3 5 7 9 1 2 3 4 5 USB2 JP4 4.4.5 AGP USB Settings (JP5 and USB2) When using AGP’s USB, these are the settings for JP5 and USB2. • Place the jumpers across JP5 pin 3 with USB2 pin 6 • Place the jumpers across JP5 pin 4 with USB2 pin 8 JP5 1 2 3 4 5 2 4 6 8 10 1 3 5 7 9 1 2 3 4 5 USB2 JP4 4.
Hardware Reference Table 20. Processor DIP Switch Settings (Sheet 2 of 2) Switch On/Off Description Default ON Use Onboard Codec OFF Disable Onboard Codec Default -- Reserved Default Off 7 8 NOTE: If you want to use SW1: 3-4 to set CPU frequency, SW1: 1-2 must be set at off.
BIOS Quick Reference 5 The evaluation board is licensed with a single copy of Embedded BIOS and Embedded DOS software from General Software, Inc.1 This software is provided for demonstration purposes only and must be licensed directly from General Software, Inc. for integration with new designs. General Software may be reached at (800) 850-5755, on the Web at http://www.gensw.com, or via e-mail at sales@gensw.com.
BIOS Quick Reference When a keyboard and video device are attached, the system can display either a traditional character-based PC BIOS display with memory count-up, or it can display a graphical POST with splash screen and progress icons. Both POST screens accept a key-press to enter the setup screen, and both display boot-time progress activity.
BIOS Quick Reference Figure 7. Graphical POST When the system is powered on for the first time, you’ll need to configure the system through the Setup Screen System (described later) before peripherals, such as disk drives, are recognized by the BIOS. The information is written to battery-backed CMOS RAM on the board’s real time clock. Should the board’s battery fail, this information will be lost and the board will need to be reconfigured.
BIOS Quick Reference 5.4 Setup Screen System The system is configured from within the Setup Screen System, which is a series of menus that can be invoked from POST by pressing the key if the main keyboard is being used, or by pressing Ctrl+C if the console is being redirected to a terminal program. Figure 8.
BIOS Quick Reference Figure 9. Embedded BIOS Basic Setup Screen 5.4.2 Configuring Drive Assignments Embedded BIOS allows the user to map a different file system to each drive letter. The BIOS allows file systems for each floppy (Floppy0 and Floppy1), each IDE drive (Ide0, Ide1, Ide2, and Ide3), and memory disks when configured (Flash0, ROM0, RAM0, etc.).
BIOS Quick Reference 5.4.3 Configuring IDE Drive Types If true IDE disk file systems (and not their emulators, such as ROM, RAM, or flash disks) are mapped to drive letters, then the IDE drives themselves must be configured in this section. The following table shows the drive assignments for Ide0-Ide3: Table 21.
BIOS Quick Reference 5.5 Configuring Boot Actions Embedded BIOS supports up to six different user-defined steps in the boot sequence. When the entire system has been initialized, POST executes these steps in order until an operating system successfully loads. In addition, other pre-boot features can be run before, after, or between operating system load attempts. The following actions can be used: 5.6 Drive A: - K: Boot operating system from specified drive.
BIOS Quick Reference Figure 10. Embedded BIOS Custom Setup Screen 5.7 Shadow Configuration Setup Screen The system’s Shadow Configuration Setup Screen (Figure 11) allows the selective enabling and disabling of shadowing in 16 Kbyte sections, except for the top 64 Kbytes of the BIOS ROM, which is shadowed as a unit. Normally, shadowing should be enabled at C000/C400 (to enhance VGA ROM BIOS performance), and then E000-F000 should be shadowed to maximize system ROM BIOS performance. Figure 11.
BIOS Quick Reference 5.8 Standard Diagnostics Routines Setup Screen Embedded systems may require automated burn-in testing in the development cycle. This facility is provided directly in the system BIOS through the Standard Diagnostics Routines Setup Screen (Figure 12). To use the system, selectively enable or disable features to be tested, and then enable the “Tests Begin on ESC?” option to cause the system test suite to be invoked.
BIOS Quick Reference 5.10 Start RS232 Manufacturing Link Setup Screen The Embedded BIOS Manufacturing Mode may be invoked from the Setup Screen main menu, as well as a boot activity. Once invoked, Manufacturing Mode takes over the system and freezes the console of the system (Figure 13). The host can resume operation of the system and give control back to the system Setup Screen system with special control software. Figure 13. Start RS232 Manufacturing Link Setup Screen 5.
BIOS Quick Reference The software on the target can be any terminal emulation program that supports ANSI terminal mode, using 9600 baud, no parity, and one stop bit (Note: This can be modified by the OEM during BIOS adaptation.) The program must be set to not use flow control, or the console may seem to stall or not accept input. Caution: 5.11.2 HYPERTERMINAL’s default setting is to use flow control, which will render the console inoperative.
BIOS Quick Reference To activate the debugger at any time from the main console, press the left shift and the control keys together. A display similar to the one in the HYPERTERMINAL session below (Figure 15) will appear, containing the title, “Embedded BIOS Debugger Breakpoint Trap” and a snapshot of the processor general registers. Figure 15.
BIOS Quick Reference A complete discussion of the debugger is beyond the scope of this chapter; however, complete documentation is available from General Software via the Web at http://www.gensw.com. 5.12 Embedded BIOS POST Codes Embedded BIOS writes progress codes, also known as POST codes, to I/O port 80H during POST, in order to provide information to OEM developers about system faults. These POST codes may be monitored on the on-board Post Code Debugger located at U12 and U13.
BIOS Quick Reference POST_STATUS_VIDEOROM POST_STATUS_POSTVIDEO POST_STATUS_CHECKEGAVGA POST_STATUS_TESTVIDEOMEMORY POST_STATUS_RETRACE POST_STATUS_ALTDISPLAY POST_STATUS_ALTRETRACE POST_STATUS_VRFYSWADAPTER POST_STATUS_SETDISPMODE POST_STATUS_CHECKSEG40A POST_STATUS_SETCURSOR POST_STATUS_PWRONDISPLAY POST_STATUS_SAVECURSOR POST_STATUS_BIOSIDENT POST_STATUS_HITDEL POST_STATUS_VIRTUAL POST_STATUS_DESCR POST_STATUS_ENTERVM POST_STATUS_ENABINT POST_STATUS_CHECKWRAP1 POST_STATUS_CHECKWRAP2 POST_STATUS_HIGHPATT
BIOS Quick Reference POST_STATUS_BEFORESETUP POST_STATUS_CALLSETUP POST_STATUS_POSTSETUP POST_STATUS_DISPPWRON POST_STATUS_DISPWAIT POST_STATUS_ENABSHADOW POST_STATUS_STDCMOSSETUP POST_STATUS_MOUSE POST_STATUS_FLOPPY POST_STATUS_CONFIGFLOPPY POST_STATUS_IDE POST_STATUS_CONFIGIDE POST_STATUS_CHECKSEG40G POST_STATUS_CHECKSEG40H POST_STATUS_SETMEMSIZE POST_STATUS_SIZEADJUST POST_STATUS_INITC8000 POST_STATUS_CALLC8000 POST_STATUS_POSTC8000 POST_STATUS_TIMERPRNBASE POST_STATUS_SERIALBASE POST_STATUS_INITBEFOREN
BIOS Quick Reference 5.13 Embedded BIOS Beep Codes Embedded BIOS tests much of the system hardware early in POST before messages can be displayed on the screen. When system failures are encountered at these early stages, POST uses beep codes (a sequence of tones on the speaker) to identify the source of the error. The following is a comprehensive list of POST beep codes for the system BIOS.
Bill of Materials A Table 22. Bill of Materials (Sheet 1 of 10) Rev. 1.1 Reference Designator Manuf.
Bill of Materials Table 22. Bill of Materials (Sheet 2 of 10) Rev. 1.
Bill of Materials Table 22. Bill of Materials (Sheet 3 of 10) Rev. 1.1 Reference Designator Y2 Description Manufacturer X’TAL KDS Manuf. Part Number Alternate Manufacturing Info 32.768KHZ EPSON 32.768KHZ, CITIZEN 32.768KHZ DIMM1,DIMM2,DIMM3 SOCKET MOLEX DIMM UNBUFFERED 168PIN 3.3V NYLON FOXCONN DIMM UNBUFFERED 168PIN 3.3V, TEKCON DIMM UNBUFFERED 168PIN 3.
Bill of Materials Table 22. Bill of Materials (Sheet 4 of 10) Rev. 1.1 Reference Designator 68 Description Manufacturer Manuf. Part Number Alternate Manufacturing Info All Changes WAFER 20*2PIN CUT PIN20(?) IDE1,IDE2 HEADER FAN1,FAN2,FAN3 HEADER MOLEX WAFER W/LOCK 3P ATXPR1 CON. WIESON MINI FIT CON.20PIN TEKCON MINI FIT CON.20PIN(NE W) USB1 CON. FOXCONN USB CON. 2*4 PIN DUAL PORT MOLEX USB CON. 2*4 PIN DUAL PORT(NEW), WIESON USB CON.
Bill of Materials Table 22. Bill of Materials (Sheet 5 of 10) Rev. 1.1 Reference Designator Description Manufacturer Manuf. Part Number Alternate Manufacturing Info RN19,RN20,RN69 R.P 22 OHM (8P 4R) CONCAVE 22 OHM (8P 4R) - CONVEX RN34 R.P 33 OHM (8P 4R) CONCAVE 33 OHM (8P 4R) - CONVEX RN3,RN5,RN6,RN7,RN 8,RN9,RN10, R.P 56 OHM (8P 4R) CONCAVE 56 OHM (8P 4R) - CONVEX RN11,RN12,RN13,RN1 4,RN15,RN16,RN17,R N18,RN21,RN22,RN23, RN24,RN25,RN26,RN2 7,RN28,RN29,RN30,R N31,RN32,RN33 R.
Bill of Materials Table 22. Bill of Materials (Sheet 6 of 10) Rev. 1.1 Reference Designator 70 Description Manufacturer Manuf.
Bill of Materials Table 22. Bill of Materials (Sheet 7 of 10) Rev. 1.1 Reference Designator Description Manuf. Part Number Manufacturer R149,R162,R213 RESISTOR 10M (0603) PR14 RESISTOR 15 OHM (1%) 0603 R31 RESISTOR 22 OHM (1%) 0603 R56 RESISTOR 33 OHM (1%)0603 PR9,PR15,PR18,PR27 RESISTOR 40.2 OHM (1%)0603 PR41 RESISTOR 60.4 OHM (1%)0603 PR7,PR10,PR11,PR12, PR42 RESISTOR 75 OHM (1%)0603 PR21,PR24 RESISTOR 82 OHM (1%)0603 R33,R61 RESISTOR 90.
Bill of Materials Table 22. Bill of Materials (Sheet 8 of 10) Rev. 1.1 Reference Designator 72 Manuf. Part Number Description Manufacturer RT1 THERMISTO R SEMITEC C11,C14,C26,C60,C64, C67,C71 CAPACITOR 0.001UF (0603) BC26,BC28,BC29,BC3 2,BC33, BC46BC48,BC51,BC52,BC5 5,BC57, BC59,BC62,BC63,BC6 5,BC74,BC75, BC79,BC80,BC82,BC8 7,BC88, BC90BC98,BC105,BC114,B C119, BC124,BC144, BC147,BC149,BC150, BC158-BC160,BC169BC171, BC181BC183,BC186,BC187,B C222, BC226,C17,C85 CAPACITOR 0.
Bill of Materials Table 22. Bill of Materials (Sheet 9 of 10) Rev. 1.1 Reference Designator Description Manuf. Part Number MC36,MC37,MC38,MC 39,MC40,MC41, MC42,MC43,MC44,MC 45,MC47,MC53, MC54,MC56,C5,C8,C1 3,C15,C18,C91, C104,C113 CAPACITOR 1UF (0603) MC48,MC57,MC59,C1, C2,C115 CAPACITOR 2.2UF (0805) MC1-MC6,MC8MC10,MC13-MC15 CAPACITOR 4.
Bill of Materials Table 22. Bill of Materials (Sheet 10 of 10) Rev. 1.1 Manuf. Part Number Alternate Manufacturing Info TAYEH 22UF/16V (4*7) JACKCON 22UF/16V (4*7) E/C TAYEH 100UF/16V (6.3*7) JACKCON 100UF/16V (6*7) C6 T/C SPRAGUE 33UF/20V "D" EC1,EC2,EC4,EC7,EC 8,EC9,EC12,EC13, E/C TAYEH 1500UF/ 6.3V(8*16) EC14,EC21,EC23,EC2 4,EC25,EC29, E/C JACKCON 1500UF/ 6.3V(8*16) EC31,EC32,EC34,C32 E/C JPCON 1500UF/6.
Bill of Materials Table 23. Key Components Bill of Materials Rev. 1.
Schematics B Schematics are provided for the following items listed below. Schematics are available from the Intel Developer’s Web site in PDF format.
1 2 3 4 B C D E ABIT SL30 A 25 26 27 28 29 ATX POWER & H/W MONITOR VOLTAGE REGULATOR PART 1 VOLTAGE REGULATOR PART 2 SYSTEM CONFIGURATION B C D **PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE 32 24 FRONT PANEL & CNR HISTORY 23 KB, MS, GAME & IR 30 22 WOR, WOL & 2S1P 31 21 LPC I/O CONTROLLER & FDCL DECOUPLING CAPACITORS 20 AUDIO I/O PU/PDR & UNUSED GATES 19 14 AC97 CODEC 12,13 PCI 1 & 2 18 11 ICH PART 1 & 2 USB 0-3 10 AGP 17 9 DIMM 3 FWH & UDMA100 IDE 1-2 7
1 2 ABIT SL30 A IDE Primary Floopy FirmWare Hub USB PORT 1-4 USB B Game Port UDMA/100 ADDR IDE Secondary ADDR Mouse Keyboard SIO ICH2 GMCH CTRL Digital Video Out Device Serial 1 GTL BUS 3 DIMM Modules CLOCK C Serial 2 Parallel Audio Codec CNR &RQQHFWRU PCI ADDR/DATA PCI CNTRL C AC’97 LINK 370-PIN SOCKET PROCESSOR BLOCK DIAGRAM CTRL AGP Connector VRM B DATA 3 4 A Term.
A B C D RS#0 RS#1 RS#2 ABIT SL30 5,7 5,7 5,7 5 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 RS#0 RS#1 RS#2 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#1
A B C D CPU_PWGD CPURST# ABIT SL30 12 7 12 APICD0 12 APICD1 6 APICCLK_CPU 6 CPUHCLK ITPRDY# ITPCLK 6 5 DBRESET# 26 5 R315 0 J2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 HEADER 15X2 150,1% BC7 0.1UF MC7 4.7UF 150,1% PR4 4 10PF C12 22 R275 86 243 VCC2_5 150 R6 VTT1_5 330 R13 R33 150 R14 R319 PR6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2.7K 1K 150 R199 R15 VCC2_5 R314 VTT1_5 4 150 R7 243 VTT1_5 47 330 R8 X18PF Place Site w/in 0.
A B C D HA#6 HA#8 HA#11 HA#4 HA#18 HA#26 HA#29 HA#27 56/8P4R RN16 2 4 6 8 56/8P4R RN18 2 4 6 8 56/8P4R RN28 2 4 6 8 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 3,7 HREQ#1 MC22 4.7UF 0.1UF 0.1UF 5 BC35 BC34 0.1UF BC36 4,7 BNR# " One Cap for each 2 R-Pack " ABIT SL30 4.
1 2 3 4 ABIT SL30 A MEMCLK0 MEMCLK1 MEMCLK2 MEMCLK3 13,22,28 SLP_S3# 9,10,13,22,25,30 SMBCLK 9,10,13,22,25,30 SMBDATA 29 FMOD0 12 PCLK_0/ICH 13 ICH_CLK14 13 ICH_3V66 8 GMCH_3V66 11 AGPCLK_CONN 29 FMOD1 VCC2_5 VCC3SBY VCC3SBY 1 1 1 X10PF X10PF C40 10 0.1UF X10P/8P4C MEMCLK4 MEMCLK5 MEMCLK6 MEMCLK7 VCC3_3 C39 R60 4.7UF X10PF CN4 4.7UF 1 X10PF C41 0.01UF 0.1UF 33 33 33 33 33 10 R67 R290 R72 0.1UF MEMCLK8 MEMCLK9 MEMCLK10 MEMCLK11 4.7UF B 0.1UF X10PF C34 0.
A B C D 4 GTLREF HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 5 K2 L1 H1 C38 X18PF RS#0 RS#1 RS#2 Do Not Stuff C Place Site w/in 0.
A B C D GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# ADSTB0 ADSTB0# ADSTB1 ADSTB1# SBSTB SBSTB# ST0 ST1 ST2 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 ABIT SL30 40,1% PR15 5 PR14 U7C HCLK HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HUBREF HLSTB HLSTB# HCOMP VSYNC HSYNC RED GREEN BLUE DCLKREF IWASTE IREF DDDA DDCK LTVCK LTVDA LTVDATA0 LTVDATA1 LTVDATA2 LTVDATA3 LTVDATA4 LTVDATA5 LTVDATA6 LTVDATA7 LTVDATA8 LTVDATA9 LTVDATA10 LTVDATA11 BLANK# TVCLKIN/SL_STALL CL
1 2 3 4 SM_MAB#[4..7] SM_CKE[0..3] 7 SM_BS0 SM_BS1 7,10 7,10 CH6-12 ABIT SL30 6,10,13,22,25,30 SMBDATA 6,10,13,22,25,30 SMBCLK SM_RAS# SM_CAS# 7,10 7,10 SM_WE# 7,10 7 SM_CSB#[0..3] 7 SM_CSA#[0..3] MEMCLK[0..7] 6 7,10 SM_DQM[0..7] 7 7,10 SM_MD[0..63] 7,10 SM_MAA[0..12] A A SMBDATA SMBCLK SM_BS1 SM_BS0 SM_CAS# SM_RAS# SM_WE# SM_CSB#[0..3] SM_CSA#[0..3] SM_CKE[0..3] MEMCLK[0..7] SM_DQM[0..7] SM_MAB#[4..7] SM_MD[0..63] SM_MAA[0..
1 2 3 4 SM_MAC#[4..7] SM_CKE[4..5] 7 SM_BS0 SM_BS1 7,9 7,9 ABIT SL30 A 9 DM_SA_PU 6,9,13,22,25,30 SMBDATA 6,9,13,22,25,30 SMBCLK SM_RAS# SM_CAS# 7,9 7,9 SM_WE# 7,9 7 SM_CSB#[4..5] 7 SM_CSA#[4..5] MEMCLK[8..11] 6 7,9 SM_DQM[0..7] 7 7,9 SM_MD[0..63] 7,9 SM_MAA[0..12] A SMBDATA SMBCLK SM_BS1 SM_BS0 SM_CAS# SM_RAS# SM_WE# SM_CSB#[4..5] SM_CSA#[4..5] SM_CKE[4..5] MEMCLK[8..11] SM_DQM[0..7] SM_MAC#[4..7] SM_MD[0..63] SM_MAA[0..
1 2 3 4 1 3 5 7 1 3 5 7 ADSTB0 ADSTB0# ADSTB1 ADSTB1# SBSTB SBSTB# RBF# CH6-18 A 1 3 5 7 SBA4 SBA5 SBA6 SBA7 ABIT SL30 1 3 5 7 SBA0 SBA1 SBA2 SBA3 1 3 5 7 ST0 ST1 ST2 1 3 5 7 1 3 5 7 GFRAME# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# WBF# 1 3 5 7 GIRDY# GDEVSEL# GPERR# GSERR# A 8.2K/8P4R 8.2K/8P4R RN45 2 4 6 8 8.2K/8P4R RN47 2 4 6 8 8.2K/8P4R RN46 2 4 6 8 8.2K/8P4R RN44 2 4 6 8 8.2K/8P4R RN43 2 4 6 8 8.2K/8P4R RN42 2 4 6 8 8.
A B C D GPIO23 GPIO27 GPIO28 18 30 30 5 ICH_IRQ#E ICH_IRQ#F ICH_IRQ#G ICH_IRQ#H P66DET S66DET GPI8 EXTSMI# LPC_PME# 30 30 30 30 18 18 30 25 22,30 ABIT SL30 PCI_REQ#A PCLK_0/ICH FRAME# DEVSEL# IRDY# TRDY# STOP# ICHRST# PLOCK# PAR SERR# PERR# PCI_PME# C_BE#0 C_BE#1 C_BE#2 C_BE#3 AD[0..
1 2 3 4 ABIT SL30 A A 6 USBP0P USBP0N USBP1P USBP1N USBP2P USBP2N USBP3P USBP3N USBOC#0-1 USBOC#2-3 EE_CS EE_DIN EE_DOUT EE_SHCLK 19 19 19 19 19 19 19 19 19 19 25 25 25 25 VCC5 ICH_CLK14 BATTERY BAT1 JP1 10M Y2 10M C96 RN71 15/8P4R 1 2 3 4 5 6 7 8 560K R271 CP1 22 18,22 18,22 18,22 18,22 18,22 25,29 20,25 20,25 20,25,29 X18PF 20,25,30 25,30 25,29 C88 6 6 560K 47PF/8P4C R164 OVT# SLP_S3# SLP_S5# PWROK GPIO25 22 PWRBTN# 23,30 ICH_RI# 22 RSMRST# 22,30 6,22,28 28 22,26 30
1 2 3 4 SERR# AD[0..31] ABIT SL30 12,15 C_BE#[0..3] 12,15 15,30 ACK64# 12,15,30 12,15,30 PLOCK# 12,15,30 PERR# 12,15,30 DEVSEL# IRDY# PREQ#0 12,30 12,15,30 PCLK_1 6 11,15,30 PIRQ#B 15,30 PIRQ#D ACK64# AD1 AD5 AD3 AD8 AD7 AD12 AD10 C_BE#1 AD14 PERR# AD17 C_BE#2 AD21 AD19 C_BE#3 AD23 AD27 AD25 AD31 AD29 A C_BE#[0..3] AD[0..
1 2 3 4 SERR# AD[0..31] ABIT SL30 12,14 C_BE#[0..3] 12,14 14,30 ACK64# 12,14,30 12,14,30 PLOCK# 12,14,30 PERR# 12,14,30 DEVSEL# IRDY# PREQ#2 12,14,30 PCLK_3 6 12,30 14,30 PIRQ#D 11,14,30 PIRQ#B A A C_BE#[0..3] AD[0..
A B C D LEFT BLANK ABIT Computer Corp. Date: Size B Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number 16 of 32 Rev A E Sheet 1 1 ABIT SL30 Title 2 2 This Page Is Left Blank.
1 2 3 4 ABIT SL30 VID_BLUE 3VDDCDA 3VDDCCL CRT_HSYNC CRT_VSYNC 3VFTSDA 3VFTSCL 8 8 8 8 8 8 8 FTD[0..11] VID_GREEN 8 8 VID_RED 8 A 7,18,22,30 PCIRST# A FTD[0..11] 3.3PF C43 FTD9 FTD10 FTD11 FTD6 FTD7 FTD8 FTD3 FTD4 FTD5 FTD0 FTD1 FTD2 3 4 7 8 11 14 17 18 21 22 1 13 1 3.3PF C47 1 3.
A B C D LAD0 LAD1 LAD2 13,22 13,22 13,22 8 ABIT SL30 GPIO23 12 7,17,22,30 PCIRST# 8 R206 0.1UF BC173 7 8.2K VCC3_3 7 0 R207 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FWH32 VPP RST# FGPI3 FGPI2 FGPI1 FGPI0 WP# TBL# ID3 ID2 ID1 ID0 FWH0 FWH1 FWH2 GND U23 FWH 6 VCC CLK FGPI4 IC GNDA VCCA GND VCC INIT# FWH4 RFU RFU RFU RFU RFU FWH3 6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC3_3 R211 0.1UF BC175 5 8.2K 0.1UF BC177 5 LAD3 INIT# LFRAME# PCLK_8 0.
A B C D AGPUSBN AGPUSBP 11 11 8 ABIT SL30 CNRUSBN CNRUSBP 25 25 USBOC#2-3 13 USBP2N USBP2P USBP3N USBP3P AGP_OC# 13 13 13 13 CNR_OC# 11 USBP0N USBP0P USBP1N USBP1P USBOC#0-1 25 13 13 13 13 13 8 X0 X0 7 RN73 15K/8P4R R269 R268 R266 R267 330K 330K V3SB RN72 15K/8P4R 7 1 3 5 7 2 4 6 8 1 3 5 7 2 4 6 8 F7 VCC5DUAL F4 VCC5DUAL 6 FUSE_1.0A FUSE_1.
A B C 8 ABIT SL30 25 AC97SPKR 21 LNLVL_OUT_R 21 LNLVL_OUT_L 21 AUX_L 21 AUX_R 21 CD_R 21 CD_L 21 CD_REF 21 LINE_IN_R 21 LINE_IN_L 21 MIC_IN 7 7 R154 10K R155 1K 6 0.1UF BC141 6 MC58 MC56 X1UF 1UF 5 5 C94 MC53 PC_BEEP LINE_IN_R LINE_IN_L MIC1 MIC2 CD_R CD_L CD_REF VIDEO_R VIDEO_L AUX_L AUX_R PHONE MONO_OUT LINE_OUT_R LINE_OUT_L LNLVL_OUT_R LNLVL_OUT_L 2700PF 2700PF 1UF C95 12 24 23 21 22 20 18 19 17 16 14 15 13 37 36 35 41 39 0.
A B C D LINE_IN_L 20 MIC_IN 8 ABIT SL30 20 20 AUD_VREFOUT LINE_IN_R 20 20 EAPD 20 LNLVL_OUT_R 20 LNLVL_OUT_L 8 1UF MC41 1UF 7 100PF 100PF C85 0.01UF 1K R120 2.
A B C D 8 ABIT SL30 8 VCC5 VCCRTC THRMDN VCC5 -5VIN -12VIN +12VIN +3.
1 2 3 4 PAR_INIT# SLIN# STB# PDR0 PDR1 PDR2 PDR3 SLCT PDR4 PE PDR5 BUSY PDR6 PDR7 ACK# 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 A ERR# 22 ABIT SL30 AFD# ICH_RI# 22 13,30 11,12,14,15 PCI_PME# A RI1 RI0 100 R229 4.7K R230 10K R109 10K R107 R110 2.2K R108 2.
1 2 3 4 JOY2Y JOY1Y J2BUTTON2 J1BUTTON2 MIDI_IN 22 22 22 22 22 IRRX 22 A MCLK 22 ABIT SL30 IRTX MDAT 22 22 KCLK KDAT 22 22 MIDI_OUT 22 VCC5DUAL J1BUTTON1 J2BUTTON1 JOY1X JOY2X 22 22 22 22 A C67 1000PF C71 1000PF C63 22PF C65 22PF IR1 RN4 8 6 4 2 F2 R18 F1 0 0 IR HEADER_1X5 1 2 3 4 5 C68 22PF R17 C66 22PF C64 1000PF R91 RN40 8 6 4 2 XFUSE_1.0A 4.
A B C D BEEP 22 AC97SPKR 8 ABIT SL30 20 13,29 ICH_SPKR SUSLED HWRST# 26 22 IDEACTS# 18 PANSWIN 22 IDEACTP# EXTSMI# 18 KEYLOCK# 22 12 8 2 4 R256 0 XHEADER 2X2 1 3 JP2 R255 10K VCC5 0.1UF BC185 R223 10K VCC5 R241 10K 7 R226 7 Q20 2N3904 R231 68 68 Q22 2N3904 R234 150 VCC5SBY 1N4148 1N4148 R232 D14 D15 R240 0 R242 R244 220 10K VCC5SBY 0 BC184 0.
1 2 3 4 PS_ON VCCRTC FANPWM2 FANPWM1 R213 R16 R216 ABIT SL30 S1 10M 510 510 A HEADER_2PIN If case is opened, this switch should be closed. 13,22 CASEOPEN# 22 22 4 DBRESET# 25 HWRST# 22 A Q1 2N7002 R10 4.7K R11 Q17 2N7002 1K 1K 4.
1 2 3 ABIT SL30 A 11 EC32 + VCC1_8 VTT1_5 TYPEDET# 1500UF 1500UF EC34 + VDDQ 13 VRM_PWRGD 1500UF EC31 + L4 1500UF EC25 + R31 22 B R32 1K Q10 HUF75307D3S TO-252 7UH R191 R56 1500UF 33 100UF EC30 + 14 15 19 18 16 10 11 HIP6020 VSEN4 DRIVE4 VSEN3 DRIVE3 VAUX VSEN2 SELECT PHASE2 UGATE2 OCSET2 U4 10 R36 VCC12 VID0 VID1 VID2 VID3 VID4 SS COMP1 FB1 VSEN1 PGND LGATE1 PHASE1 UGATE1 OCSET1 1K R53 VCC3_3 "SINGLE POINT CONNECTION 1K 2 1 9 1UF R55 VCC3
1 2 3 4 ABIT SL30 A VCC5 VCC3_3 VCC5SBY 6,13,22 SLP_S3# 13 SLP_S5# V3SB A C18 1UF EC20 + 10UF NZT651/SOT223 Q4 EC15 + 100UF EC22 + 100UF 0.1UF C7 6 7 5 2 13 B 0.
C R153 1.8K R260 8.2K R261 8.2K R262 8.2K R263 8.2K D SW2:7-8 ON BOARD AC97 CODEC ON 7 PRIMARY CODEC DISABLE ON 8 PRI_DWN_RST# 20 6 6 13,20,25 13,25 7 R_REFCLK FMOD0 FMOD1 AC_SDOUT ICH_SPKR 7 R_BSEL#0 E Rev 4 1 Date: B Size Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet SYSTEM CONFIGURATION ABIT Computer Corp.
1 2 3 4 PERR# SERR# PLOCK# STOP# DEVSEL# TRDY# IRDY# FRAME# A ICH_IRQ#E ICH_IRQ#F ICH_IRQ#G ICH_IRQ#H 12 12 12 12 ABIT SL30 ICH_IRQ#A ICH_IRQ#B ICH_IRQ#C ICH_IRQ#D 12 12 12 12 PIRQ#A PIRQ#B PIRQ#C PIRQ#D ACK64# REQ64#1 REQ64#2 REQ64#3 14,15 14 14 15 11,14,15 11,14,15 14,15 14,15 PREQ#3 PREQ#5 PREQ#4 12 12 12 12,15 PREQ#2 12,14 PREQ#1 12,14 PREQ#0 12,14,15 12,14,15 12,14,15 12,14,15 12,14,15 12,14,15 12,14,15 12,14,15 SMBALERT# ICH_RI# SMBCLK SMBDATA PCI_REQ#A OVT# KBRST# A20GATE GPI8 GP
1 2 3 4 MC5 4.7UF MC31 MC30 MC11 4.7UF MC16 4.7UF BC66 0.1UF 0.1UF MC24 4.7UF BC71 0.1UF BC78 0.1UF 0.01UF 0.01UF 0.1UF 0.1UF 8 7 6 5 ABIT SL30 HOLE A 0.1UF 0.1UF H1 1 2 3 4 BC107 BC100 " misc. " BC132 BC131 VCC3_3 0.01UF BC80 0.01UF BC74 0.1UF A BC106 0.1UF BC138 0.1UF BC109 0.1UF BC121 " ICH : 0.1U//0.01U at each conner " BC82 BC87 VCC3_3 0.1UF BC39 4.7UF MC14 0.1UF BC53 0.1UF H3 1 2 3 4 BC122 0.01UF BC150 0.01UF BC88 0.
A B C D HISTORY ABIT Computer Corp. Date: Size B Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number 32 of 32 Rev A E Sheet 1 1 ABIT SL30 Title 2 2 This Page Is Left Blank.
Index #, defined 7 A I I/O Controller Hub (ICH2) 24 Instructions, notational conventions 7 Accelerated Graphics Port (AGP) Support 12 M B Baseboard Features 11 Beep codes 49, 64 BIOS Basic Setup Screen 52 Configuring floppy drives 53 Configuring IDE drives 54 Console redirection 58 Custom Setup Screen 55 Drive assignments 53 Integrated BIOS debugger 59 Setup Screen System 51 Shadow Configuration Setup Screen 56 Standard Diagnostics Routines Setup Screen 57 BlueCat™ Linux 14 C Chipset 11 clock generatio
