Datasheet

22 Intel
®
815E Scalable Performance Board Development Kit Manual
Theory of Operation
3.2 Mechanical Design
The evaluation board conforms to the micro-ATX form factor. For extra protection in a
development environment, you may want to install the evaluation board in an ATX chassis. The
evaluation board has three 32 bit/33 MHz PCI connectors, one AGP connector, one CNR
connector, three SDRAM DIMM connectors, and one ABIT V-Bus connector. The system I/O
connectors are in the rear of the board in the defined micro-ATX I/O window.
3.3 Thermal Management
The objective of thermal management is to ensure that the temperature of each component is
maintained within specified functional limits. The functional temperature limit is the range within
which the electrical circuits can be expected to meet their specified performance requirements.
Operation outside the functional limit can degrade system performance and cause reliability
problems.
The development kit is shipped with a heatsink/fan thermal solution pre-installed on the processor
using metal clips. This thermal solution has been tested in an open air environment at room
temperature and is sufficient for evaluation purposes. The designer must ensure that adequate
thermal management is provided for any customer-derived designs.
3.4 System Operation
The Intel
®
815E Scalable Performance Board Development Kit is designed to support Intel
®
Celeron
™
processors (566 MHz and above) and Intel
®
Pentium
®
III processors up to 1 GHz in the
flip chip-grid array (FC-PGA) package. The 815E chipset includes the GMCH, ICH2, and the
FWH.
3.4.1 Intel
®
Pentium
®
III Processor
The Intel
®
Pentium
®
III processor is a member of the P6 family in the Intel
®
IA-32 processor line.
Like the Intel
®
Pentium
®
II processor, the Intel
®
Pentium
®
III processor implements the Dynamic
Execution microarchitecture — a unique combination of multiple branch prediction, data flow
analysis, and speculative execution. Intel
®
Pentium
®
III processor features include the following:
• Dynamic Execution technology
• Includes Intel MMX media enhancement technology
• Intel streaming SIMD extensions
• Incorporates separate 16 Kbyte level-one caches (32 Kbytes total); one for instructions and
one for data
• 256 Kbytes integrated, full-speed level two cache with error correcting code (ECC)
• 8-way level two cache associativity, which provides improved cache-hit rate on read/store
operations
• Double quad word-wide (256 bit) cache data bus, which provides extremely high throughput
on read/store operations