TECHNICAL MANUAL LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller October 2005 Version 3.
This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited.
Preface This book is the primary reference and technical manual for the LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller. It contains a complete functional description for the LSISAS1064, as well as the physical and electrical specifications for the LSISAS1064. Audience This document assumes that you are familiar with microprocessors and related support devices.
• Appendix A, Register Summary, provides a register map for the LSISAS1064. Related Publications LSI Logic Documents Fusion-MPT™ Device Management User’s Guide, Version 2.0, DB15-000186-02 LSI Logic World Wide Web Home Page www.lsilogic.com ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 InterNational Committee on Information Technology Standards (INCITIS) T10 Technical Committee http://www.t10.
Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Signals that are active LOW end with a “/.” Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111. Revision History Revision Date Remarks Final Version 3.2 9/2005 Updated external memory diagrams.
vi Preface Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Contents Chapter 1 Chapter 2 Introduction 1.1 General Description 1.2 Benefits of SAS 1.3 Benefits of the Fusion-MPT Architecture 1.4 Benefits of PCI-X 1.5 Benefits of GigaBlaze® Transceivers 1.6 Summary of LSISAS1064 Features 1.6.1 SAS Features 1.6.2 SATA Features 1.6.3 PCI Performance 1.6.4 Integration 1.6.5 Usability 1.6.6 Flexibility 1.6.7 Reliability 1.6.8 Testability 1-1 1-4 1-5 1-6 1-7 1-7 1-7 1-8 1-8 1-9 1-10 1-10 1-10 1-11 Functional Description 2.1 Block Diagram Description 2.1.
2.4 2.5 2.6 2.7 2.8 Chapter 3 Chapter 4 Chapter 5 viii SAS Functional Description External Memory Interface 2.5.1 Memory Requirements 2.5.2 Flash ROM Controller 2.5.3 NVSRAM Controller Zero Channel RAID Universal Asynchronous Receiver/Transmitter (UART) Multi-ICE Test Interface 2-17 2-19 2-19 2-20 2-22 2-23 2-24 2-25 Signal Description 3.1 Signal Organization 3.2 PCI Signals 3.2.1 PCI System Signals 3.2.2 PCI Address and Data Signals 3.2.3 PCI Interface Control Signals 3.2.
5.4 5.5 Appendix A Pinout Package Drawings 5-12 5-20 Register Summary Index Customer Feedback Contents Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
x Contents Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Figures 1.1 1.2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.1 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.
xii Contents Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Tables 2.1 2.2 2.3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.1 5.2 5.3 5.4 5.5 5.
5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 5.31 5.32 A.1 A.2 A.
Chapter 1 Introduction The LSISAS1064 is a four-port 3.0 Gbit/s SAS/SATA controller that is compliant with the Fusion-MPT™ architecture, provides a PCI-X interface, and supports the Integrated RAID™ solution. This chapter contains the following sections: 1.1 • Section 1.1, “General Description” • Section 1.2, “Benefits of SAS” • Section 1.3, “Benefits of the Fusion-MPT Architecture” • Section 1.4, “Benefits of PCI-X” • Section 1.5, “Benefits of GigaBlaze® Transceivers” • Section 1.
version 1.0a. SATA II is an extension to SATA 1.0a. LSI Logic SAS/SATA controllers also support the following SATA II features: • 3.0 Gbit/s SATA • Staggered spin-up • Hot Plug • Native Command Queuing • Activity and fault indicators per phy • Port Selector (for dual-port drives) Supporting both the SAS and SATA interfaces, the LSISAS1064 is a versatile controller that provides the backbone of both server and highend workstation environments.
Figure 1.1 LSISAS1064 Direct-Connect Example Application Tx , Rx SAS/SATA Device Tx , Rx SAS/SATA Device Tx , Rx SAS/SATA Device 32-bit Memory Address/Data Bus LSISAS1064 64-Bit, 133 MHz PCI-X Controller Flash ROM/ PSBRAM/ NVSRAM I2C Interface I2C Tx , Rx SAS/SATA Device PCI/PCI-X Interface Figure 1.
The LSISAS1064 is based on the Fusion-MPT (Message Passing Technology) architecture, which features a performance based message passing protocol that off loads the host CPU by completely managing all I/Os and minimizes system bus overhead by coalescing interrupts. The Fusion-MPT architecture requires only a thin, easy to develop device drivers that is independent of the I/O bus. LSI Logic provides these device drivers. The LSISAS1064 supports a 32-bit external memory bus.
advantages of SATA, SCSI, and FC, and is the future mainstay of the enterprise and high-end workstation storage markets. SAS offers a higher bandwidth per pin than parallel SCSI, and improves signal and data integrity. The SAS interface uses the proven SCSI command set to ensure reliable data transfers, while providing the connectivity and flexibility of point-topoint serial data transfers. The serial transmission of SCSI commands eliminates clock skew challenges.
The Fusion-MPT architecture improves overall system performance by requiring only a thin device driver, which off loads the intensive work of managing I/Os from the system processor to the LSISAS1064. The use of thin, easy to develop, common OS device drivers accelerates time to market by reducing device driver development and certification times. The Fusion-MPT architecture provides an interrupt coalescing feature.
transaction information with all PCI-X transactions to enable more efficient buffer management schemes. Each PCI-X transaction contains a transaction sequence identifier (Tag), the identity of the initiator, and the number of bytes in the sequence. The LSISAS1064 clocks PCI-X data directly into and out of registers, which creates a more efficient data path.
1.6.2 • Provides 4 fully independent phys • Each phy supports 3.0 Gbits/s and 1.
1.6.4 – Supports 32-bit or 64-bit addressing through Dual Address Cycles (DAC) – Provides a theoretical 1066 Mbytes/s PCI bandwidth – Supports 3.3 V PCI, and is not 5 V PCI tolerant – Complies with the PCI Local Bus Specification, Revision 3.0 – Complies with the PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0 – Complies with the PCI Power Management Interface Specification, Revision 1.
1.6.5 • Provides a full 32-bit or 64-bit PCI-X DMA bus master • Reduces time to market with the Fusion-MPT architecture – Single driver binary for SAS/SATA, SCSI, and Fibre Channel products – One firmware build supports all Integrated RAID capabilities – Thin, easy to develop drivers – Reduced integration and certification effort Usability This section describes the usability features. 1.6.
1.6.
1-12 Introduction Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Chapter 2 Functional Description This chapter provides a subsystem level overview of the LSISAS1064, a discussion of the Fusion-MPT architecture, and a functional description of the LSISAS1064 interfaces. This chapter contains the following sections: • Section 2.1, “Block Diagram Description” • Section 2.2, “Fusion-MPT Architecture Overview” • Section 2.3, “PCI Functional Description” • Section 2.4, “SAS Functional Description” • Section 2.5, “External Memory Interface” • Section 2.
2.1 Block Diagram Description The LSISAS1064 consists of two major modules and a context RAM. The two major modules are the host interface module and the Quad Port module.
Figure 2.
2.1.1.1 PCI/PCI-X Interface The LSISAS1064 provides a PCI-X interface that supports up to a 64-bit, 133 MHz PCI-X bus. The LSISAS1064 PCI interface is backward compatible with previous implementations of the PCI specification, with the exception that the LSISAS1064 does not support 5 V PCI. For more information on the PCI interface, refer to Section 2.3, “PCI Functional Description.” 2.1.1.2 System Interface In combination with the IOP, the system interface supports the Fusion-MPT architecture.
2.1.1.4 PCI Timer and Configuration This PCI Timer and Configuration module supports the PCI configuration register space, an industry-standard and a power-on reset (POR). 2.1.1.5 Timer and Configuration This block supports the LSISAS1064 LED and GPIO interfaces. There are a total of nine LED signals on the LSISAS1064. Each of the four phys has an LED signal to indicate activity on the link and an LED signal to indicate an error on the link. The GPIO interface contains four independent GPIO signals.
two-wire serial interface chip. The I2C block controls all bus timing and performs bus-specific sequences. 2.1.1.9 UART The UART provides test and debug access to the LSISAS1064. 2.1.2 Quad Port The Quad Port module in the LSISAS1064 implements the SSP, SMP, and STP/SATA protocols, and manages the four SAS/SATA PHYs. The following subsections describe the Quad Port module. Refer to Section 2.4, “SAS Functional Description,” for an operational description of the LSISAS1064 SAS ports. 2.1.2.
2.1.2.5 SAS Link and Phy The LSISAS1064 uses the Gflx GigaBlaze transceivers to implement the SAS link. The SAS link layer manages SAS connections between initiator and target ports, data clocking, and CRC checking on received data. The SAS link is also responsible for starting a link reset sequence. The SAS phys interface to the physical layer, perform serial-to-parallel conversion of received data and parallel-to-serial conversion of transmit data, manage phy reset sequences, and perform 8b/10b encoding.
queue consists of the request post FIFO. The reply message queue consists of both the reply post FIFO and the reply free FIFO. The context RAM contains the message queues. The Fusion-MPT architecture also provides a High Priority Request FIFO to provide high priority request free messages to the host on reads and to accept high priority request post messages from the host on writes. Communication using the message queues occurs through request messages and reply messages.
2.3.1 PCI Addressing The three physical address spaces the PCI specification defines are: • PCI Configuration Space • PCI I/O Space for operating registers • PCI Memory Space for operating registers The following sections describe the PCI address spaces. 2.3.1.1 PCI Configuration Space The PCI Configuration Space is a contiguous 256 x 8-bit set of addresses. The system BIOS initializes the configuration registers using PCI configuration cycles.
2.3.1.3 PCI Memory Space The LSISAS1064 contains two PCI memory spaces: PCI Memory Space [0] and PCI Memory Space [1]. PCI Memory Space [0] supports normal memory accesses while PCI Memory Space [1] supports diagnostic memory accesses. The LSISAS1064 requires 64 Kbytes of memory space. The PCI specification defines memory space as a contiguous 64-bit memory address that all system resources share.
Table 2.1 PCI/PCI-X Bus Commands and Encodings1 (Cont.) C_BE[3:0]/ PCI Command PCI-X Command Supports as Master Supports as Slave Split Completion Yes Yes2 0b1100 Memory Read Multiple 0b1101 Dual Address Cycle Dual Address Cycle Yes Yes 0b1110 Memory Read Line Memory Read Block Yes Yes2 0b1111 Memory Write and Invalidate Memory Write Block Yes Yes3 1. The LSISAS1064 ignores reserved commands as a slave and never generates them as a master. 2.
2.3.2.5 Memory Read Command The LSISAS1064 uses the Memory Read command to read data from an agent mapped in the memory address space. The target can perform an anticipatory read if such a read produces no side effects. The LSISAS1064 supports this command when operating in the PCI bus mode. 2.3.2.6 Memory Read Dword Command The Memory Read Dword command reads up to a single Dword of data from an agent mapped in the memory address space and can only be initiated as a 32-bit transaction.
LSISAS1064 by asserting its IDSEL signal when AD[1:0] equal 0b00. During the address phase of a configuration cycle, AD[7:2] address one of the 64 Dword registers in the configuration space of each device. C_BE[3:0]/ address the individual bytes within each Dword register and determine the type of access to perform. Bits AD[10:8] address the PCI function Configuration Space (AD[10:8] = 0b000). The LSISAS1064 treats AD[63:11] as logical don’t cares. 2.3.2.
transactions when operating in the PCI-X mode. A split transaction consists of at least two separate bus transactions: a split request, which the requester initiates, and one or more split completion commands, which the completer initiates. Revision 2.0 of the PCI-X addendum permits split transaction completion for the Memory Read Block, Alias to Memory Read Block, Memory Read Dword, Interrupt Acknowledge, I/O Read, I/O Write, Configuration Read, and Configuration Write commands.
Alignment – The LSISAS1064 uses the calculated line size value to determine if the current address aligns to the cache line size. If the address does not align, the LSISAS1064 bursts data using a noncache command. If the starting address aligns, the LSISAS1064 issues a Memory Write and Invalidate command using the cache line size as the burst size. Multiple Cache Line Transfers – The Memory Write and Invalidate command can write multiple cache lines of data in a single bus ownership.
2.3.5 PCI Interrupts The LSISAS1064 signals an interrupt to the host processor either using PCI interrupt pins (INTA/ and ALT_INTA/), or Message Signaled Interrupts (MSI and MSI-X). The Interrupt Request Routing Mode bits in the Host Interrupt Mask register configure the routing of each interrupt to either the INTA/ and/or the ALT_INTA/ pin. MSI is an optional feature that enables a device to signal an interrupt by writing to a specified address.
2.4 SAS Functional Description The LSISAS1064 provides four SAS/SATA phys. Each phy can form one side of the physical link in a connection with a phy on a different SAS/SATA device. The physical link contains four wires that form two differential signal pairs. One differential pair transmits signals, while the other differential pair receives signals. Both differential pairs operate simultaneously, and allow concurrent data transmission in both the receive and the transmit directions. Figure 2.
Figure 2.3 Narrow and Wide Links a. Narrow Link Containing One Phy in each Port Narrow Port Phy Narrow Port TX Phy RX b. Wide Link Containing Three Phys in each Port Wide Port Phy Wide Port TX Phy RX Phy TX Phy RX Phy TX Phy RX Each phy on the LSISAS1064 can function as an SSP Initiator, an SSP target, an SMP initiator, an STP initiator, or a SATA Initiator. A phy can function in only one role during a connection, but function in different roles during different connections.
Figure 2.4 SAS Initiator SSP, STP, and SMP Protocol Usage SMP Initiator SAS Initiator SAS Initiator STP SMP SSP SATA SAS Expander SATA SAS Target 2.5 SMP Target SATA Target SATA Target External Memory Interface The external memory control block provides a direct slave interface between the internal primary AHB bus and an external 32-bit memory interface. This interface is for accessing external Flash ROM and NVSRAM devices.
– • The LSISAS1064 has no memory requirements in this configuration, assuming that the intelligent IOP can download the firmware image to the LSISAS1064 and store the persistent data. Integrated RAID implementation – The LSISAS1064 requires a Flash ROM for Integrated RAID implementations. – The LSISAS1064 requires an NVSRAM for all Integrated Mirroring implementations. The LSISAS1064 does not require a PSBRAM for any board design or application. 2.5.
• Uniform sector and/or boot block sector • 64 Kbyte maximum sector size • Intel/Sharp extended command set and/or AMD/Fujitsu extended command set programming algorithms The Fusion-MPT firmware for the LSISAS1064 supports all CFI Flash parts and a limited set of non-CFI Flash parts. Contact the LSI Logic or OEM representative for a current list of supported non-CFI Flash parts. Figure 2.5 provides a diagram of a Flash ROM configuration.
Table 2.2 Flash ROM Signature Value (Cont.) Flash ROM Address 2.5.3 Flash ROM Signature Values Bytes [7:4] 0x5A 0xEA 0xA5 0x5A Bytes [11:8] 0xA5 0x5A 0xEA 0xA5 Bytes [15:12] 0x5A 0xA5 0x5A 0xEA NVSRAM Controller The LSISAS1064 provides a NVSRAM interface that supports write journaling in Integrated Mirroring applications or provides memory space for firmware code overflow.
Figure 2.6 NVSRAM Block Diagram Upper Address MAD[23:16] MAD[15:8] XM_Address[15:8] Lower Address MAD[7:0] MAD[31:24] 2.6 XM_Address[7:0] XM_Data[7:0] NVSRAM_CS/ CE/ MOE[0]/ OE/ BWE[2]/ WE/ NVSRAM (up to 4M x 8) XM_Address[23:16] Middle Address Zero Channel RAID Zero channel RAID (ZCR) capabilities enable the LSISAS1064 to respond to accesses from a PCI RAID controller card or chip that is able to generate ZCR cycles.
Figure 2.7 ZCR Circuit Diagram for the LSISAS1064 ZCR PCI Slot Vdd Int A/ (A6) Int B/ (B7) Int C/ (A7) Int D/ (B8) 0.1 kΩ Vdd Vdd 4.7 kΩ 4.7 kΩ LSISAS1064 TDI (A4) GNT/ (A17) ALT_INTA/ IDSEL (A26) AD21 (B29) ZCR_EN/ ALT_GNT/ Vdd 0.1 kΩ IDSEL Host System Int A/ Int B/ Int C/ Int D/ AD21 220 Ω AD19 Note: To maintain proper interrupt mapping, select the address line for use as IDSEL on the LSISAS1064 to be +2 address lines above IDSEL on ZCR slot. 2.
2.8 • Does not support 5-bit and 6-bit characters • Does not support 1.5 stop bits • Provides additional registers to support the speed sense logic • Provides a synchronous interface to allow access to internal registers and FIFOs Multi-ICE Test Interface Include a 20-pin header to access the ARM Multi-ICE signals through the ICE JTAG post. The header has a 100 mil spacing between posts. The connector is a 20-way header that mates with IDC sockets that are mounted on a ribbon cable.
2-26 Functional Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Chapter 3 Signal Description This chapter describes the input and output signals of the LSISAS1064, and consists of the following sections: • Section 3.1, “Signal Organization” • Section 3.2, “PCI Signals” • Section 3.3, “PCI-Related Signals” • Section 3.4, “Compact PCI Signals” • Section 3.5, “SAS Signals” • Section 3.6, “Memory Interface Signals” • Section 3.7, “Communication Signals” • Section 3.8, “Configuration and General Purpose Signals” • Section 3.
• SAS Interface • Memory Interface • Communication Interface • Configuration and GPIO Interface • JTAG and Test Interface There are five signal types: I Input, a standard input-only signal O Output, a standard output driver (typically a Totem Pole output) I/O Input and output (bidirectional) P Power G Ground Figure 3.1 contains the functional signal groupings of the LSISAS1064. Figure 5.8 on page 5-18 provides a diagram of the LSISAS1064 472 Ball Grid Array (BGA). Table 5.31 and Table 5.
Figure 3.
3.2 PCI Signals This section describes the PCI signals. 3.2.1 PCI System Signals Table 3.1 describes the PCI system signals. Table 3.1 PCI System Signals Signal Name BGA Position Type Description CLK Y4 I RST/ W5 I Refer to the PCI Local Bus Specification, Version 3.0, and the PCI-X Addendum to the PCI Local Bus Specification, Version 2.0, for complete signal descriptions. 3.2.2 PCI Address and Data Signals Table 3.1 describes the PCI address and data signals. Table 3.
3.2.3 PCI Interface Control Signals Table 3.3 describes the PCI interface control signals. Table 3.3 PCI Interface Control Signals Signal Name BGA Position Type Description ACK64/ AE18 I/O REQ64/ AD18 I/O Refer to the PCI Local Bus Specification, Version 3.0, and the PCI-X Addendum to the PCI Local Bus Specification, Version 2.0, for complete signal descriptions. FRAME/ AB7 I/O IRDY/ AF6 I/O TRDY/ AA9 I/O DEVSEL/ AD5 I/O STOP/ AE6 I/O IDSEL AD3 I 3.2.
3.2.6 PCI Interrupt Signals Table 3.6 describes the PCI interrupt signals. Table 3.6 PCI Interrupt Signals Signal Name BGA Position Type Description INTA/ V3 Refer to the PCI Local Bus Specification, Version 3.0, and the PCI-X Addendum to the PCI Local Bus Specification, Version 2.0, for complete signal descriptions. 3.3 O PCI-Related Signals Table 3.7 describes the PCI-related signals. Table 3.
3.4 Compact PCI Signals Table 3.8 describes the CompactPCI signals. Table 3.8 CompactPCI Signals Signal Name BGA Position Type Description CPCI_EN/ R1 I Asserting active LOW CompactPCI Enable configures the LSISAS1064 for the CompactPCI protocol. CPCI_SWITCH P1 I The active HIGH CompactPCI Switch signal indicates to the LSISAS1064 that a change in the system configuration is imminent. The CompactPCI device insertion/removal mechanism controls the assertion of this signal.
3.6 Memory Interface Signals Table 3.10 describes the memory interface signals. Table 3.10 Memory Interface Signals Signal Name BGA Position Type Description MCLK N26 O All synchronous RAM control/data signals reference the rising edge of the Memory Clock signal. MOE[1:0]/ are asynchronous inputs and do not reference this clock. ADSC/ P23 O Asserting the active LOW Address-Strobe-Controller signal initiates read, write, or chip deselect cycles.
Table 3.10 Memory Interface Signals (Cont.) Signal Name BGA Position Type Description PSBRAM_CS/ J24 O Asserting the active LOW RAM Chip Select signal selects the PSBRAMs. The LSISAS1064 supports up to four PSBRAMs in an interleaved and depth-expanded configuration. FLASH_CS/ O Asserting the active LOW Flash Chip Select signal selects the Flash ROM. The LSISAS1064 maps the Flash ROM address space into system memory. 3.7 H26 Communication Signals Table 3.11 describes the UART and I2C signals.
3.8 Configuration and General Purpose Signals Table 3.12 describes the configuration and general purpose signals. Table 3.12 Configuration and General Purpose Signals Signal Name BGA Position Type Description TST_RST/ G7 I Asserting the Test Reset signal forces the chip into a Power-On-Reset state. The LSISAS1064 does not contain an internal power-on reset circuit. This signal must be supplied by a power-on reset circuit on the board. REFCLK_B D3 I This pin provides the ARM reference clock.
3.9 JTAG and Test Signals Table 3.13 describes the test and JTAG signals. Table 3.13 Test and JTAG Signals Signal Name BGA Position Type Description TCK L2 I JTAG Debug Clock. TRST/ L1 I JTAG Debug Reset. TDI J1 I JTAG Debug Test Data In. TDO K1 O JTAG Debug Test Data Out. TMS P2 I JTAG Debug Test Mode Select. TCK_ICE B5 I Multi-ICE Debug Clock. RTCK_ICE A5 O Multi-ICE Debug Return Clock. TRST_ICE/ C5 I Multi-ICE Debug Reset.
3.10 Power Signals Table 3.14 describes the power and ground signals. Table 3.14 Power and Ground Signals Signal Name BGA Position Type Description REFPLL_VDD D2 P These signals provide 1.2 V power. REFPLL_VSS C1 G These signals provide ground. PLL_VDD AC4 P These signals provide 1.2 V power. PLL_VSS AC3 G These signals provide ground. VDD2 C11, C12, D10, M13, M15, N12, P N14, P13, P15, R12, R14 These signals provide 1.2 V core power.
Table 3.14 Power and Ground Signals (Cont.
Table 3.
• MAD[28:17], Reserved. • MAD[16], PCI-X Operation – Pulling this signal LOW enables the PCI-X operation. Pulling this signal HIGH disables PCI-X operation. • MAD[15], 133 MHz PCI-X Operation – Pulling this signal LOW enables 133 MHz PCI-X operation. Pulling this signal HIGH disables 133 MHz PCI-X operation. • MAD[14], 64-bit PCI Operation – Pulling this signal LOW enables 64-bit PCI operation. Pulling this signal HIGH disables 64-bit PCI operation.
3.12 Internal Pull-Ups and Pull-Downs Table 3.16 describes the pull-up and pull-down signals for the LSISAS1064. Table 3.16 Pull-Up and Pull-Down Conditions Signal Name BGA Position Pull Type MODE[5:0] C2, F4, D1, E3, E2, F3 Internal Pull-down. MAD[31:0] AB26, AA25, R22, W26, V24, V25, Internal Pull-down. AA26, U24, T22, Y26, R23, U25, R26, T24, T26, V26, H24, K24, H23, H21, D23, C26, E25, D25, D24, D26, E24, C24, C25, G23, F23, B26 MADP[3:0] W23, P26, J26, G21 Internal Pull-up.
Chapter 4 PCI Host Register Description This chapter describes the PCI host register space. This chapter consists of the following sections: • Section 4.1, “PCI Configuration Space Register Description” • Section 4.2, “PCI I/O Space and Memory Space Register Description” The register map at the beginning of each register description provides the default bit settings for the register. Shading indicates a reserved bit or register. Do not access the reserved address areas.
Pointer registers and identify the extended capability structure with the Capability ID register for the given structure. Table 4.
Register: 0x00–0x01 Vendor ID Read Only 15 8 7 0 Vendor ID 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Vendor ID [15:0] This 16-bit register identifies the manufacturer of the device. The Vendor ID is 0x1000. Register: 0x02–0x03 Device ID Read Only 15 8 7 0 Device ID 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 Device ID [15:0] This 16-bit register identifies the particular device. The default Device ID for the LSISAS1064 is 0x0050.
Interrupt Disable 10 Clearing this bit enables the PCI function to assert its interrupt signal (INTA/). Setting this bit disables the PCI function from asserting its interrupt signal. Fast Back-to-Back Enable 9 This bit determines if the master can perform fast backto-back transactions to different devices. Clearing this bit indicates that fast back-to-back transactions are permitted to only the same device.
Enable Memory Space 1 This bit controls the ability of the PCI function to respond to Memory Space accesses. Setting this bit allows the LSISAS1064 to respond to Memory Space accesses at the address range specified by the Memory [0] Low, Memory [0] High, Memory [1] Low, Memory [1] High, and the Expansion ROM Base Address registers. Clearing this bit disables the PCI function’s response to PCI Memory Space accesses.
Received Target Abort (from Master) A master device sets this bit when a Target Abort command terminates its transaction. 12 Signaled Target Abort 11 The target device must set this bit when it terminates a transaction with a target abort command. DEVSEL/ Timing [10:9] These two read only bits encode the timing of DEVSEL/ and indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSISAS1064 only supports medium DEVSEL/ timing.
New Capabilities 4 The LSISAS1064 PCI function sets this read only bit to indicate a list of PCI extended capabilities such as PCI Power Management, MSI, MSI-X, and PCI-X support. Interrupt Status 3 This bit reflects the status of the INTA/ (or ALT_INTA/) signal. Reserved This field is reserved. [2:0] Register: 0x08 Revision ID Read/Write 7 0 Revision ID x x x x x x x x Revision ID [7:0] This register indicates the current revision level of the device.
Register: 0x0C Cache Line Size Read/Write 7 0 Cache Line Size 0 0 0 0 0 0 0 0 Cache Line Size [7:3] This register specifies the system cache line size in units of 32-bit words. In the conventional PCI mode, the LSISAS1064 PCI function uses this register to determine whether to use Write and Invalidate or Write commands for performing write cycles. Programming this register to a number other than a nonzero power of two disables the the use of the PCI performance commands to execute data transfers.
Register: 0x0E Header Type Read Only 7 0 Header Type 0 0 0 0 0 0 0 0 Header Type [7:0] This 8-bit register identifies the layout of bytes 0x10 through 0x3F in configuration space and also indicates if the device is a single function or multifunction PCI device. Since the LSISAS1064 is a single function PCI device, bit 7 is cleared. Register: 0x0F Reserved 7 0 Reserved 0 0 0 0 0 0 0 0 Reserved This register is reserved.
Reserved This field is reserved. [1:0] Register: 0x14–0x17 Memory [0] Low Read/Write 31 24 23 16 15 8 7 0 0 0 Memory [0] Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 The Memory [0] Low register and the Memory [0] High register map SCSI operating registers into Memory Space [0]. This register contains the lower 32 bits of the Memory Space [0] base address.
Register: 0x1C–0x1F Memory [1] Low Read/Write 31 24 23 16 15 8 7 0 0 0 Memory [1] Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 The Memory [1] Low register and the Memory [1] High register map the RAM into Memory Space [1]. This register contains the lower 32 bits of the Memory Space [1] base address.
Register: 0x24–0x27 Reserved 31 24 23 16 15 8 7 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved This register is reserved. 0 0 [31:0] Register: 0x28–0x2B Reserved 31 24 23 16 15 8 7 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved This register is reserved.
Register: 0x2E–0x2F Subsystem ID Read Only 15 8 7 0 Subsystem ID x x x x x x x x x x x x x x x x Subsystem ID [15:0] This 16-bit register uniquely identifies the add-in board or subsystem where this PCI device resides. This register provides a mechanism for an add-in card vendor to distinguish their cards from one another even if the cards use the same PCI controller (and have the same Vendor ID and Device ID).
This four-byte register contains the base address and size information for the expansion ROM. Expansion ROM Base Address [31:11] These bits correspond to the upper 21 bits of the expansion ROM base address. The host system detects the size of the external memory by first writing 0xFFFFFFFF to this register and then reading the register back. The LSISAS1064 responds with zeros in all don’t care locations. The least significant one (1) that remains represents the binary version of the external memory size.
Register: 0x35–0x37 Reserved 23 16 15 8 7 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved This register is reserved. 0 0 [23:0] Register: 0x38–0x3B Reserved 31 24 23 16 15 8 7 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved This register is reserved.
Register: 0x3D Interrupt Pin Read Only 7 0 Interrupt Pin 0 0 0 0 0 0 0 1 Interrupt Pin [7:0] This read only register indicates which interrupt pin the PCI function uses. This register is set to 0x01, which indicates that PCI function presents interrupts on the INTA/ or ALT_INTA/ pins. The Interrupt Request Routing Mode bits, bits [9:8] in the Host Interrupt Mask register, determine if the function presents interrupts on INTA/, ALT_INTA/, or both.
Max_Lat [7:0] This register specifies the desired settings for the latency timer values in units of 0.25 µs. Max_Lat specifies how often the device needs to gain access to the PCI bus. The LSISAS1064 sets this register to 0x0A since it requires the PCI bus every 2.5 µs. Register: 0xXX Power Management Capability ID Read Only 7 0 Power Management Capability ID 0 0 0 0 0 0 0 1 Power Management Capability ID [7:0] This register indicates the type of the current data structure.
PME_Support [15:11] These bits define the power management states in which the device asserts the Power Management Event (PME) pin. The LSISAS1064 clears these bits since the LSISAS1064 does not provide a PME signal. D2_Support 10 The PCI function sets this bit since the LSISAS1064 supports power management state D2. D1_Support The PCI function sets this bit since the LSISAS1064 supports power management state D1.
PME_Status 15 The PCI function clears this bit since the LSISAS1064 does not support PME signal generation from D3cold. Data_Scale [14:13] The PCI function clears these bits since the LSISAS1064 does not support the Power Management Data register. Data_Select [12:9] The PCI function clears these bits since the LSISAS1064 does not support the Power Management Data register. PME_Enable 8 The PCI function clears this bit since the LSISAS1064 does not provide a PME signal and disables PME assertion.
Register: 0xXX Power Management Data Read Only 7 0 Power Management Data 0 0 0 0 0 0 0 0 Power Management Data [7:0] This register provides an optional mechanism for the PCI function to report state-dependent operating data. The LSISAS1064 always returns 0x00 in this register. Register: 0xXX MSI Capability ID Read Only 7 0 MSI Capability ID 0 0 0 0 0 1 0 1 MSI Capability ID [7:0] This register indicates the type of the current data structure.
Register: 0xXX MSI Message Control Read/Write 15 8 7 0 MSI Message Control 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 Reserved This field is reserved. 0 [15:9] Per-Vector Masking Capable 8 If this bit is set, the device supports MSI per-vector masking. If this bit is cleared, the function does not support MSI per-vector masking. This bit is read only. 64-Bit Address Capable The PCI function sets this read only bit to indicate support of a 64-bit message address.
Multiple Message Capable [3:1] These read only bits indicate the number of messages that the LSISAS1064 requests from the host. The host system software reads this field to determine the number of requested messages. The number of requested messages must align to a power of two. The LSISAS1064 sets this field to 0b000 to request one message. All other encodings of this field are reserved. MSI Enable 0 System software sets this bit to enable MSI.
Register: 0xXX MSI Message Upper Address Read/Write 31 24 23 16 15 8 7 0 0 0 MSI Message Upper Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSI Message Upper Address [31:0] The LSISAS1064 supports 64-bit MSI message. This register contains the upper 32 bits of the 64-bit message address, which the system specifies. The host system software can program this register to 0x0000 to force the PCI function to generate 32-bit message addresses.
Register: 0xXX MSI Mask Bits Read/Write 31 24 23 16 15 8 7 0 0 0 MSI Mask Bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSI Mask Bits [31:0] For each mask bit that is set, the device is prohibited from sending an associated message. Refer to the PCI specification for a complete description of this register.
Register: 0xXX MSI-X Next Pointer Read Only 7 0 MSI-X Next Pointer x x x x x x x x MSI-X Next Pointer [7:0] This register points to the next item in the extended capabilities list. The value of this register varies according to system configuration. Register: 0xXX MSI-X Message Control Read/Write 15 8 7 0 MSI-X Message Control 0 0 0 0 0 x x x x x x x x x x x MSI-X Enable 15 Setting this bit enables the device to use MSI-X to request service from the host.
Register: 0xXX MSI-X Table Offset Read Only 31 24 23 16 15 8 7 x x 0 MSI-X Table Offset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x MSI-X Table Offset [31:3] This field provides an offset from the address held in the base address registers of the device to the base of the MSI-X table.
Register: 0xXX MSI-X PBA Offset Read Only 31 24 23 16 15 8 7 x x 0 MSI-X PBA Offset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x MSI-X PBA Offset [31:3] This field contains an offset from one of the base address registers of the device that points to the MSI-X PBA. The lower 3 bits of this register are cleared (‘0’) for a 32-bit aligned offset.
Register: 0xXX PCI-X Next Pointer Read Only 7 0 PCI-X Next Pointer x x x x x x x x PCI-X Next Capabilities Pointer [7:0] This register points to the next item in the device’s capabilities list. The value of this register varies according to system configuration. Register: 0xXX PCI-X Command Read/Write 15 8 7 0 PCI-X Command 0 0 0 1 0 0 0 0 0 1 1 0 0 Reserved This field is reserved.
Table 4.4 Bits [6:4] Encoding 0b011 Maximum Outstanding Split Transactions (Cont.) Maximum Outstanding Split Transactions 4 0b100 8 0b101 12 0b110 16 0b111 Reserved Maximum Memory Read Byte Count [3:2] These bits indicate the maximum byte count the LSISAS1064 uses when initiating a sequence with one of the burst memory read commands. Table 4.5 provides the bit encodings for this field. Table 4.
Register: 0xXX PCI-X Status Read/Write 31 24 23 16 15 8 7 x x 0 PCI-X Status 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 x x x x x x Reserved This field is reserved. x x x x x x x x [31:30] Received Split Completion Error Message 29 The LSISAS1064 sets this bit upon receipt of a split completion message if the split completion error attribute bit is set. Write a one (1) to this bit to clear it.
0b10 in this field to indicate that the designed maximum memory read bytes count is 2048. Device Complexity 20 The PCI function clears this read only bit to indicate that the LSISAS1064 is a simple device. Unexpected Split Completion 19 The PCI function sets this read only bit when it receives an unexpected split completion. Once set, this bit remains set until software clears it. Write a one (1) to this bit to clear it.
Device Number [7:3] These read only bits indicate the device number of the LSISAS1064. The PCI function uses this number as part of its Requester ID and Completer ID. This field is read for diagnostic purposes only. Function Number [2:0] These read only bits indicate the number in the Function Number field (AD[10:8]) of a Type 0 PCI configuration transaction. The PCI function uses this number as part of its Requester ID and Completer ID. This field is read for diagnostic purposes only. 4.
Table 4.6 31 PCI I/O Space Address Map 16 15 System Doorbell Write Sequence Host Diagnostic Test Base Address Diagnostic Read/Write Data Diagnostic Read/Write Address Reserved Host Interrupt Status Host Interrupt Mask Reserved Request Queue Reply Queue High Priority Request MFA Queue Reserved 0 Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018–0x002F 0x0030 0x0034 0x0038–0x003F 0x0040 0x0044 0x0048 0x004C–0x007F Page 4-34 4-34 4-35 4-37 4-37 4-38 – 4-38 4-39 – 4-40 4-41 4-41 – Table 4.
Register: 0x00 System Doorbell Read/Write 31 24 23 16 15 8 7 0 0 0 System Doorbell 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The System Doorbell register is a simple message passing mechanism that allows the system to pass single word messages to the embedded IOP processor and vice versa. When a host system PCI master writes to the Host Registers->Doorbell register, the LSISAS1064 generates a maskable interrupt to the IOP.
Reserved This field is reserved. [31:4] Write I/O Key [3:0] To enable write access to the Diagnostic Read/Write Data, Diagnostic Read/Write Address, and Host Diagnostic register, perform five data-specific writes to the Write I/O Key. Writing an incorrect value to the Write I/O Key invalidates the key sequence and the host must rewrite the entire sequence. The Write I/O Key sequence is: 0x00FF, 0x0004, 0x000B, 0x0002, 0x0007, and 0x000D.
Diagnostic Write Enable 7 The LSISAS1064 sets this read only bit when the host writes the correct Write I/O Key to the Write Sequence register. The LSISAS1064 clears this bit when the host writes a value other than the Write I/O Key to the Write Sequence register. Flash Bad Signature 6 The LSISAS1064 sets this bit if the IOP ARM966E-S™ processor encounters a bad Flash signature when booting from Flash ROM.
Register: 0x0C Test Base Address Read/Write 31 24 23 16 15 8 7 0 0 0 Test Base Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The Test Base Address register specifies the base address for Memory Space [1] accesses. Test Base Address [31:10] The number of significant bits is determined by the size of the PCI Memory Space [1] in the NVData image. Reserved This field is reserved.
Register: 0x14 Diagnostic Read/Write Address Read/Write 31 24 23 16 15 8 7 0 0 0 Diagnostic Read/Write Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The Diagnostic Read/Write Address register specifies a Dword location on the internal bus. The address increments by a Dword whenever the host system accesses the Diagnostic Read/Write Address register.
Reserved This field is reserved. [30:4] Reply Interrupt 3 The LSISAS1064 sets this bit when the Reply Post FIFO is not empty. The LSISAS1064 generates a PCI interrupt when this bit is set and the corresponding mask bit in the Host Interrupt Mask register is cleared. Reserved This field is reserved. [2:1] System Doorbell Interrupt 0 The LSISAS1064 sets this bit when the IOP writes a value to the System Doorbell. The host can clear this bit by writing any value to this register.
Table 4.9 Interrupt Signal Routing Bits [9:8] Encodings Interrupt Signal Routing 0b00 INTA/ and ALT_INTA/ 0b01 INTA/ Only 0b10 ALT_INTA/ Only 0b11 INTA/ and ALT_INTA/ Reserved This field is reserved. [7:4] Reply Interrupt Mask 3 Setting this bit masks reply interrupts and prevents the assertion of a PCI interrupt for all reply interrupt conditions. Reserved This field is reserved.
Register: 0x44 Reply Queue Read/Write 31 24 23 16 15 8 7 1 1 0 Reply Queue 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 The Reply Queue provides Reply Post MFAs to the host system on reads and accepts Reply Free MFAs from the host system on writes. Reply FIFO [31:0] For reads, this register contains the Reply Post MFA. For writes, the register contains the Reply Free MFA.
4-42 PCI Host Register Description Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Chapter 5 Specifications This chapter specifies the LSISAS1064 electrical and mechanical characteristics. It is divided into the following sections: • Section 5.1, “DC Characteristics” • Section 5.2, “AC Characteristics” • Section 5.3, “External Memory Timing Diagrams” • Section 5.4, “Pinout” • Section 5.5, “Package Drawings” Please refer to the PCI Local Bus Specification, the PCI-X Addendum to the PCI Local Bus Specification, and the Serial Attached SCSI Standard for timing information.
Table 5.1 Symbol TSTG VDD-Core VDD-IO ILP ESDHBM 1. Absolute Maximum Stress Ratings1 Parameter Min Max Unit Test Conditions Storage Temperature −65 150 °C – Supply Voltage -0.3 2.0 V – I/O Supply Voltage -0.3 3.96 V – Latch-up Current 150 – mA EIA/JESD78 Electrostatic Discharge -Human Body Model (HBM) – V JESD-A114-B 2 kV Stresses beyond those listed above can damage the device.
Table 5.4 GigaBlaze Receiver Voltage Characteristics – RX[3:0] Parameter Min Max Unit Condition Vp-p – OOB 150 – mV inside the EYE Vp-p – normal operation 275 – mV inside the EYE Table 5.5 GigaBlaze Transceiver Rise/Fall Characteristics – TX[3:0], RX[3:0] Speed and Technology Nominal Rise Nominal Fall Time Time Specified Range Unit SAS - 1.5 Gbit/s 141 153 67 - 273 psec SAS - 3.0 Gbit/s 129 125 67 - 137 psec SATA - 1.5 Gbit/s 141 141 100 - 273 psec SATA - 3.
Table 5.8 Parameter Min Max Unit Condition Vol – 0.1 × VDDIO V Iout = 1500 µA Voh 0.9 × VDDIO – V Iout = -500 µA Ioz -10 10 µA – Table 5.9 Inputs – ZCR_EN/, CPCI_EN/, TN/, UART_RX Parameter Min Max Unit Vil VSS - 0.5 0.8 V Vih 2 VDD + 0.3 V Iin -10 10 µA Ipull-up 70 200 µA Table 5.10 Inputs – CPCI_SWITCH, MODE[5:0], SCAN_ENABLE, SCAN_MODE Parameter Min Max Unit Vil VSS - 0.5 0.8 V Vih 2 VDD + 0.3 V Iin -10 10 µA Ipull-down 70 350 µA Table 5.
Table 5.12 Schmitt Trigger Inputs – REFCLK_B, FSELA Parameter Min Nom Max Units VT+ – 1.6 2 V VT- 1 1.2 – V Hysteresis 0.3 0.4 – V Iin -10 – 10 µA Ipull-down 70 140 350 µA Table 5.13 10 mA, 3-State Outputs – CPCI_LED/, HB_LED/, FAULT_LED[3:0]/, ACTIVE_LED[3:0]/ Parameter Min Max Unit Vol – 0.4 V Voh 2.4 – V Ioz -10 10 µA Table 5.14 5 mA, 3-State Outputs – TDO, TDO_ICE, RTCK_ICE Parameter Min Max Unit Vol – 0.4 V Voh 2.
Table 5.17 Parameter Min Max Unit Vol – 0.4 V Voh 2.4 – V Ioz -10 10 µA Table 5.18 8 mA Bidirectional Signals – MAD[31:0] Parameter Min Max Unit Vil VSS - 0.5 0.8 V Vih 2 VDD + 0.3 V Vol – 0.4 V Voh 2.4 – V Ioz -10 10 µA Ipull-down 70 350 µA Table 5.19 8 mA Bidirectional Signals – MADP[3:0] Parameter Min Max Unit Vil VSS - 0.5 0.8 V Vih 2 VDD + 0.3 V Vol – 0.4 V Voh 2.4 – V Ioz -10 10 µA Ipull-up 70 200 µA Table 5.
Table 5.21 5 mA Bidirectional Signals – SERIAL_CLK, SERIAL_DATA, ISTWI_CLK, ISTWI_DATA, GPIO[3:0], TMUX_SPARE[7:0] Parameter Min Max Unit Vil VSS - 0.5 0.8 V Vih 2 VDD + 0.3 V Vol – 0.4 V Voh 2.4 – V Ioz -10 10 µA Ipull-up 70 200 µA Table 5.22 Parameter Min Nominal Max Unit Vin_cm 1.6 2.0 2.4 V Vin_diff_pp 0.6 – 2.0 V Vil 0.6 – 2.1 V Vih 1.9 – 3.4 V Iin -10 – 10 µA Table 5.23 1.
5.2 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to Section 5.1, “DC Characteristics.”) Chip timing is based on simulation at worst case voltage, temperature, and processing. Timing was developed with a load capacitance of 50 pF, which does not include the PCI/PCI-X pads. The PCI/PCI-X pads are specified as 10 pF loads. Figure 5.1 and Table 5.24 provide external clock timing data. Figure 5.
Figure 5.2 and Table 5.25 provide reset input timing data. Figure 5.2 Reset Input CLK t2 t1 RST/ t3 t4 Valid Data MAD* *When enabled Table 5.25 Reset Input Symbol Parameter Min Max Unit 10 – ns t1 Reset pulse width t2 Reset deasserted setup to CLK HIGH 0 – ns t3 MAD setup time to CLK HIGH (for configuring the MAD bus only) 20 – ns t4 MAD hold time from CLK HIGH (for configuring the MAD bus only) 20 – ns Figure 5.3 and Table 5.26 provide Interrupt Output timing data.
5.3 External Memory Timing Diagrams This section provides timing information and examples for the external memory options available for use with the LSISAS1064. Table 5.27 Symbol Flash Write Timing Parameters Parameter Min Max Unit 20 – ns t4 Flash Address Setup to FLASH_CS/ (Write) t5 Flash Address Setup to BWE/ (Write Enables) 10 – ns t6 FLASH_CS/ Width (Write) 60 400 ns t7 Flash Write Recover 40 – ns – Flash ROM Write Cycle Time 120 460 ns Min Max Unit Figure 5.
Figure 5.5 Flash Read MA A(00) A(01) MD[31:24] D0 A(10) A(11) D3 D2 D1 A=4(00) t1 t2 FLASHCS/ t3 MOE1/ BWE3/ Table 5.29 Symbol NVRAM Read Timing Parameters Parameter Min Max Unit t1 NVRAM Address Setup to NVRAM_CS/ (Read) 10 – ns t2 NVRAM_CS/ Width (Read) 15 400 ns t3 NVRAM Read Recover (back-to-back access) 10 – ns – NVRAM Read Cycle Time 25 420 ns Figure 5.
Table 5.30 Symbol NVRAM Write Timing Parameters Parameter Min Max Unit 10 – ns t4 NVRAM Address Setup to NVRAM_CS/ (Write) t5 NVRAM Address Setup to BWE/ (Write Enables) 10 – ns t6 NVRAM_CS/ Width (Write) 15 400 ns t7 NVRAM Write Recover 0 40 ns – NVRAM Write Cycle Time 25 460 ns Figure 5.7 NV Write MA A(00) MD[31:24] A(01) D0 t4 A(10) D2 D1 t4 A(11) A=4(00) D3 t6 NVRAMCS/ t5 t5 t7 BWE2/ MOE/ 5.4 Pinout Table 5.31 provides the signal listing by signal name.
Table 5.
Table 5.31 Listing by Signal Name (Cont.
Table 5.
Table 5.32 Listing by Pin Number (Cont.
(This page left intentionally blank.) Pinout Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Figure 5.
Figure 5.
5.5 Package Drawings The LSISAS1064 is packaged in a 472-EPBGA-T package with a 27 mm x 27 mm footprint and 1.0 mm ball pitch. The package code is UO. The package drawing number is JZ02-000015-00. Figure 5.9 provides the package diagram for the LSISAS1064. 5-20 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Figure 5.9 472-Pin EPBGA-T (UO) Mechanical Drawing (Sheet 1 of 3) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO. Package Drawings Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Figure 5.9 472-Pin EPBGA-T (UO) Mechanical Drawing (Sheet 2 of 3) (Cont.) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO. 5-22 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Figure 5.9 472-Pin EPBGA-T (UO) Mechanical Drawing (Sheet 3 of 3) (Cont.) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO. Package Drawings Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
5-24 Specifications Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Appendix A Register Summary Tables A.1, A.2, and A.3 provide a register summary. Table A.
Table A.1 LSISAS1064 PCI Configuration Space Registers (Cont.
Table A.1 LSISAS1064 PCI Configuration Space Registers (Cont.) Register Name Offset1 Read/Write Page MSI-X Table Offset – Read Only 4-26 MSI-X PBA Offset – Read Only 4-27 PCI-X Capability ID – Read Only 4-27 PCI-X Next Pointer – Read Only 4-28 PCI-X Command – Read/Write 4-28 PCI-X Status – Read/Write 4-30 1. The offset of the PCI extended capabilities registers can vary. Access these registers through the Next Pointer and Capability ID registers. Table A.
Table A.
Index Numerics B 133 MHz capable bit 4-31 133 MHz PCI-X 1-1, 3-14, 3-15, 5-8 133 MHz PCI-X bit 4-31 16550 UART 2-24 33 MHz PCI 5-8 64-bit address capable bit 4-21 64-bit device bit 4-31 64-bit PCI 1-1, 3-14, 3-15 66 MHz capable bit 4-6 66 MHz PCI 3-14, 3-15, 5-8 66 MHz PCI-X 5-8 ball grid array 5-18, 5-19 base address register I/O 2-4, 4-9 memory [0] 4-10 memory [1] 4-11 BGA top view 5-18, 5-19 BIOS 2-9 BIR 4-26 bit 133 MHz capable 4-31 64-bit address capable 4-21 64-bit device 4-31 66 MHz capable 4-6 a
enable bus mastering 4-4 enable I/O 4-5 enable memory space 4-5 enable parity error response 4-4 expansion ROM enable 4-14 flash ROM bad signature 4-36 function number 4-32 interrupt request routing mode 4-39 IOP doorbell status 4-38 MSI enable 4-22 multiple message 4-22 new capabilities 4-7 per-vector masking capable 4-21 PME clock 4-18 PME enable 4-19 PME status 4-19 PME support 4-18 power management version 4-18 power state 4-19 received master abort (from master) 4-5 received split completion error mess
DC characteristics 5-1 designed maximum cumulative read size bit 4-30 designed maximum memory read byte count bit 4-30 designed maximum outstanding split transactions bit 4-30 detected parity error (from slave) bit 4-5 device complexity bit 4-31 device driver stability 1-6 device ID configuration 3-14, 3-15 device ID register 4-3 device number bit 4-32 device specific initialization bit 4-18 DEVSEL/ 3-5, 5-3 DEVSEL/ timing bit 4-6 diagnostic memory 4-32 diagnostic memory enable bit 4-36 diagnostic read/writ
I I/O base address 4-5 base address register 2-4, 2-9, 4-9 key 4-35, 4-36, 4-38 processor 2-4, 2-23 read command 2-10, 2-11, 2-14 space 2-9, 4-1, 4-32 supply voltage 5-2 write command 2-10, 2-11, 2-14 I/O supply current 5-2 ICE 2-25 ID control 4-13 IDD-Core 5-2 IDD-I/O 5-2 IDDTN 3-11, 3-16 IDSEL 2-9, 3-5, 5-3 input reset 5-9 INTA/ 2-16, 3-6, 4-22, 4-25, 4-36, 4-39, 5-3 integrated RAID 1-1, 1-4 interface external memory 2-19 interrupt 2-16 acknowledge command 2-10, 2-11, 2-14 ALT_INTA/ 2-16 doorbell mask bit
memory [0] low 4-5, 4-10 memory [1] high 4-5, 4-11 memory [1] low 4-5, 4-11 memory read 4-30 memory requirements 2-19 memory space 2-10, 4-32 message passing technology 2-1 message queues 2-7, 2-8 message signaled interrupts 2-16 MFA high priority request 4-41 reply 4-41 minimum grant register 4-16 MODE[5:0] 3-10, 3-16, 5-4 MOE[1:0]/ 3-8, 5-6 MSI 2-16, 4-39 capability ID register 4-20 enable bit 4-22 mask bits 4-24 message address 4-22 message data 4-23 message upper address register 4-23 multiple message 4
memory read command 2-12 memory read dword 2-10 memory read dword command 2-12 memory read line 2-11, 2-14 memory read multiple 2-11, 2-13 memory write 2-10, 2-12 memory write and invalidate 2-11, 2-14 memory write block 2-11, 2-15 memory write command 2-12 register 4-14 special cycle 2-10, 2-11 split completion 2-11, 2-13 command register 4-3 configuration read command 2-10, 2-12, 2-14, 4-6 configuration space 2-9, 4-1 address map 4-2 C_BE[3:0]/ 2-9, 2-10 configuration write command 2-10, 2-13, 2-14, 4-6 D
split completion discarded bit 4-31 status register 4-30 unexpected split completion bit 4-31 PCI-X mode 3-14, 3-15 pending bits 4-24 PERR/ 3-5, 5-3 per-vector masking capable bit 4-21 phys 2-17 PLL_VDD 3-12 PLL_VSS 3-12 PME 4-18, 4-19 clock bit 4-18 enable bit 4-19 status bit 4-19 support bits 4-18 POR 4-36 port 2-17 POST 4-15 power management 2-16 aux_current bit 4-18 bridge support extensions register 4-19 capabilities register 4-17 capability ID register 4-17 control/status register 4-18 D0 4-19 D1 4-19
memory [1] low 4-11 minimum grant 4-16 MSI capability ID 4-20 MSI mask bits 4-24 MSI message address 4-22 MSI message control 4-21 MSI message data 4-23 MSI message upper address 4-23 MSI next pointer 4-20 MSI pending bits 4-24 MSI-X capability ID 4-24 MSI-X message control 4-25 MSI-X next pointer 4-25 MSI-X PBA offset 4-27 MSI-X table offset 4-26 PCI memory [0] address map 4-33 PCI memory [1] address map 4-33 PCI-X capability ID 4-27 PCI-X command 4-28 PCI-X next pointer 4-28 PCI-X status 4-30 power manage
ACTIVE_LED[3:0]/ 3-10 AD[63:0] 3-4 ADSC/ 3-8 ADV/ 3-8 ALT_GNT/ 3-6 ALT_INTA/ 3-6 BWE[3:0]/ 3-8 BZR_SET 3-6 BZVDD 3-6 C_BE[7:0]/ 3-4 CLK 3-4 CPCI_EN/ 3-7 CPCI_ENUM/ 3-7 CPCI_LED/ 3-7 CPCI_SWITCH 3-7 CPCI64_EN/ 3-7 DEVSEL/ 3-5 FAULT_LED[3:0]/ 3-10 FLASH_CS/ 3-9 FRAME/ 3-5 FSELA 3-10 GNT/ 3-5 GPIO[3:0] 3-10 HB_LED/ 3-10 IDDTN 3-11 IDSEL 3-5 INTA/ 3-6 IRDY/ 3-5 ISTW_CLK 3-9 ISTW_DATA 3-9 MAD[31:0] 3-8, 3-13 MADP[3:0] 3-8 MCLK 3-8 MODE[5:0] 3-10 MOE[1:0]/ 3-8 NC 3-1, 3-13 NVSRAM_CS/ 3-8 PAR 3-4 PAR64 3-4 PERR/ 3
PCI arbitration 3-5 PCI error reporting 3-5 PCI interrupt 3-6 PCI-related 3-6 power-on sense 3-13 pull-ups and pull-downs 3-16 signature recognition flash ROM 2-21 slew rate 5-8 SMP 1-2, 2-18 special cycle command 2-10, 2-11, 4-5 split completion command 2-11, 2-13 split completion discarded bit 4-31 split completion error 4-30 split completion received error message 4-30 split completion unexpected 4-31 split transaction 4-30 SSP 1-2, 2-18 standards PCI 1-2 PCI-X addendum 1-2 status IOP doorbell bit 4-38 r
V VDD_IO 5-2 VDD2 3-12 VDDC 5-2 VDDIO33 3-12 VDDIO33PCIX 3-12 VDDIO5PCIX 3-12 vendor ID register 4-3 version bit 4-18 voltage analog 5-2 core 5-2 I/O 5-2 supply 5-2 VSS2 3-12 W wide write write write port 2-17 and invalidate enable bit 4-4 I/O key 4-35, 4-36, 4-38 sequence register 4-34, 4-36, 4-38 Z ZCR 2-23, 2-24 ZCR_EN/ 2-23, 3-6, 3-16, 5-4 zero channel RAID 2-23, 2-24 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
IX-12 Index Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Customer Feedback We would appreciate your feedback on this document. Please copy the following page, add your comments, and fax it to us at the number shown. If appropriate, please also fax copies of any marked-up pages from this document. Important: Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents.
Reader’s Comments Fax your comments to: LSI Logic Corporation Technical Publications M/S AF-198 Fax: 408.433.4333 Please tell us how you rate this document: LSISAS1064 PCI-X to 4-Port Serial Attached SCSI/SATA Controller, Version 3.2. Place a check mark in the appropriate blank for each category.
