Instruction manual

3-12
MS-6593 ATX Mainboard
Configure SDRAM Timing by
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to SPD enables
SDRAM Frequency, SDRAM CAS# Latency, Row Precharge Time, RAS
Pulse Width, RAS to CAS Delay and SDRAM Bank Interleave auto-
matically to be determined by BIOS based on the configurations on the
SPD. Selecting User allows users to configure these fields manually.
SDRAM Frequency
Use this item to configure the clock frequency of the installed SDRAM.
SDRAM CAS# Latency
This controls the timing delay (in clock cycles) before SDRAM starts
a read command after receiving it. 2 (clocks) increases the system
performance the most while 3 (clocks) provides the most stable
performance.
Row Precharge Time
This item controls the number of cycles for Row Address Strobe (RAS)
to be allowed to precharge. If insufficient time is allowed for the RAS
to accumulate its charge before DRAM refresh, refresh may be in-
complete and DRAM may fail to retain data. This item applies only
when synchronous DRAM is installed in the system.
RAS Pulse Width
This setting allows you to select the number of clock cycles allotted
for the RAS pulse width, according to DRAM specifications. The less
the clock cycles, the faster the DRAM performance.
RAS to CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the
transition from RAS (row address strobe) to CAS (column address
strobe). The less the clock cycles, the faster the DRAM performance.
SDRAM Bank Interleave
This field selects 2-bank or 4-bank interleave for the installed SDRAM.
Disable the function if 16MB SDRAM is installed.