Instruction manual

AWARD
®
BIOS Setup
3-13
DRAM Timing By SPD
Selects whether DRAM timing is configured by reading the contents of the
SPD (Serial Presence Detect) device on the DRAM module. Setting to
Enabled makes both SDRAM Cycle Length and DRAM Clock automatically
determined by BIOS according to the configurations on the SPD.
SDRAM Cycle Length
The option controls the CAS latency, which determines the timing delay
before SDRAM starts a read command after receiving it. Settings: 2 and 3
(clock cycles). 2 increases system performance while 3 provides more stable
system performance.
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency. The settings are:
Host CLK The DRAM clock will be equal to the Host Clock.
Advanced Chipset Features
Note: Change these settings only if you are familiar with the chipset.