Instruction manual

Chapter 3
3-14
HCLK-33M The DRAM clock will be equal to the Host Clock minus
33MHz. For example, if the Host Clock is 133MHz, the
DRAM clock will be 100MHz.
HCLK+33M The DRAM clock will be equal to the Host Clock plus
33MHz. For example, if the Host Clock is 100MHz, the
DRAM clock will be 133MHz.
Memory Hole
In order to improve performance, certain space in memory can be reserved
for ISA cards. This memory must be mapped into the memory space below
16MB. When this area is reserved, it cannot be cached. Settings: 15M-16M
and Disabled.
P2C/C2P Concurrency
This field enables or disables the PCI to CPU and CPU to PCI concurrency
feature, which allows synchronous data transmission from PCI to CPU and
vice versa. Selecting Enabled will increase system performance.
Fast R-W Turn Around
This is used to control the fast read/write turn around feature for DRAM
timing. Settings: Enabled and Disabled. Enabled improves system per-
formance while Disabled provides stability.
System BIOS Cacheable
System BIOS ROM at F000h-F0000h is always copied to RAM for faster
execution. Selecting Enabled allows the contents of F0000h RAM memory
segment to be written to and read from cache memory, resulting in better
system performance. However, if any program writes to this memory area, a
system error may result. Settings: Enabled and Disabled.
Video RAM Cacheable
Selecting Enabled allows caching of the video memory (RAM) at A0000h-
AFFFFh, resulting in better video performance. However, if any program
writes to this memory area, a memory access error may result. Settings:
Enabled and Disabled.