Specifications

Chapter 4. Product information and technology 85
Figure 4-15 shows the physical packaging options that are supported with
POWER7 processors.
Figure 4-15 Outline of the POWER7 processor physical packaging
On-chip L3 intelligent cache
A breakthrough in material engineering and microprocessor fabrication has
enabled IBM to implement the L3 cache in eDRAM and place it on the POWER7
processor die. L3 cache is critical to a balanced design, as is the ability to
provide good signaling between the L3 cache and other elements of the
hierarchy, such as the L2 cache or SMP interconnect.
The on-chip L3 cache is organized into separate areas with differing latency
characteristics. Each processor core is associated with a Fast Local Region of L3
cache (FLR-L3), but also has access to other L3 cache regions as shared L3
cache. Additionally, each core can negotiate to use the FLR-L3 cache associated
with another core, depending on reference patterns. Data can also be cloned to
be stored in more than one core's FLR-L3 cache, again, depending on reference
patterns. This
intelligent cache management enables the POWER7 processor to
optimize the access to L3 cache lines and minimize overall cache latencies.
Single Chip Organic
1 x Memory Controller
Local broadcast SMP links active
Single Chip Glass Ceramic
2 x Memory Controllers
Local broadcast SMP links active
Global broadcast SMP links active